A new approach to pipeline FFT processor
(1996) The 10th International Parallel Processing Symposium, 1996., IPPS '96 p.766-770- Abstract
- A new VLSI architecture for a real-time pipeline FFT processor is proposed. A hardware-oriented radix-22 algorithm is derived by integrating a twiddle factor decomposition technique in the divide-and-conquer approach. The radix-22 algorithm has the same multiplicative complexity as the radix-4 algorithm, but retains the butterfly structure of the radix-2 algorithm. The single-path delay-feedback architecture is used to exploit the spatial regularity in the signal flow graph of the algorithm. For length-N DFT computation, the hardware requirement of the proposed architecture is minimal on both dominant components: log4N-1 complexity multipliers and N-1 complexity data memory. The validity and efficiency of the architecture have been... (More)
- A new VLSI architecture for a real-time pipeline FFT processor is proposed. A hardware-oriented radix-22 algorithm is derived by integrating a twiddle factor decomposition technique in the divide-and-conquer approach. The radix-22 algorithm has the same multiplicative complexity as the radix-4 algorithm, but retains the butterfly structure of the radix-2 algorithm. The single-path delay-feedback architecture is used to exploit the spatial regularity in the signal flow graph of the algorithm. For length-N DFT computation, the hardware requirement of the proposed architecture is minimal on both dominant components: log4N-1 complexity multipliers and N-1 complexity data memory. The validity and efficiency of the architecture have been verified by simulation in the hardware description language VHDL. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/1785644
- author
- He, Shousheng LU and Torkelson, Mats LU
- organization
- publishing date
- 1996
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- keywords
- pipeline processing, parallel architectures, parallel algorithms, microprocessor chips, hardware description languages, feedback, fast Fourier transforms, divide and conquer methods, discrete Fourier transforms, delay systems, VLSI, computational complexity, real-time systems
- host publication
- [Host publication title missing]
- pages
- 766 - 770
- conference name
- The 10th International Parallel Processing Symposium, 1996., IPPS '96
- conference location
- Honolulu, HI, United States
- conference dates
- 1996-04-15 - 1996-04-19
- external identifiers
-
- scopus:0029710702
- ISBN
- 0-8186-7255-2
- DOI
- 10.1109/IPPS.1996.508145
- language
- English
- LU publication?
- yes
- id
- 07e09b27-06af-489d-9230-eec81f625e2d (old id 1785644)
- date added to LUP
- 2016-04-04 14:29:17
- date last changed
- 2022-04-24 05:57:56
@inproceedings{07e09b27-06af-489d-9230-eec81f625e2d, abstract = {{A new VLSI architecture for a real-time pipeline FFT processor is proposed. A hardware-oriented radix-22 algorithm is derived by integrating a twiddle factor decomposition technique in the divide-and-conquer approach. The radix-22 algorithm has the same multiplicative complexity as the radix-4 algorithm, but retains the butterfly structure of the radix-2 algorithm. The single-path delay-feedback architecture is used to exploit the spatial regularity in the signal flow graph of the algorithm. For length-N DFT computation, the hardware requirement of the proposed architecture is minimal on both dominant components: log4N-1 complexity multipliers and N-1 complexity data memory. The validity and efficiency of the architecture have been verified by simulation in the hardware description language VHDL.}}, author = {{He, Shousheng and Torkelson, Mats}}, booktitle = {{[Host publication title missing]}}, isbn = {{0-8186-7255-2}}, keywords = {{pipeline processing; parallel architectures; parallel algorithms; microprocessor chips; hardware description languages; feedback; fast Fourier transforms; divide and conquer methods; discrete Fourier transforms; delay systems; VLSI; computational complexity; real-time systems}}, language = {{eng}}, pages = {{766--770}}, title = {{A new approach to pipeline FFT processor}}, url = {{http://dx.doi.org/10.1109/IPPS.1996.508145}}, doi = {{10.1109/IPPS.1996.508145}}, year = {{1996}}, }