Advanced

A new approach to pipeline FFT processor

He, Shousheng LU and Torkelson, Mats LU (1996) The 10th International Parallel Processing Symposium, 1996., IPPS '96 In [Host publication title missing] p.766-770
Abstract
A new VLSI architecture for a real-time pipeline FFT processor is proposed. A hardware-oriented radix-22 algorithm is derived by integrating a twiddle factor decomposition technique in the divide-and-conquer approach. The radix-22 algorithm has the same multiplicative complexity as the radix-4 algorithm, but retains the butterfly structure of the radix-2 algorithm. The single-path delay-feedback architecture is used to exploit the spatial regularity in the signal flow graph of the algorithm. For length-N DFT computation, the hardware requirement of the proposed architecture is minimal on both dominant components: log4N-1 complexity multipliers and N-1 complexity data memory. The validity and efficiency of the architecture have been... (More)
A new VLSI architecture for a real-time pipeline FFT processor is proposed. A hardware-oriented radix-22 algorithm is derived by integrating a twiddle factor decomposition technique in the divide-and-conquer approach. The radix-22 algorithm has the same multiplicative complexity as the radix-4 algorithm, but retains the butterfly structure of the radix-2 algorithm. The single-path delay-feedback architecture is used to exploit the spatial regularity in the signal flow graph of the algorithm. For length-N DFT computation, the hardware requirement of the proposed architecture is minimal on both dominant components: log4N-1 complexity multipliers and N-1 complexity data memory. The validity and efficiency of the architecture have been verified by simulation in the hardware description language VHDL. (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
pipeline processing, parallel architectures, parallel algorithms, microprocessor chips, hardware description languages, feedback, fast Fourier transforms, divide and conquer methods, discrete Fourier transforms, delay systems, VLSI, computational complexity, real-time systems
in
[Host publication title missing]
pages
766 - 770
conference name
The 10th International Parallel Processing Symposium, 1996., IPPS '96
external identifiers
  • Scopus:0029710702
ISBN
0-8186-7255-2
DOI
10.1109/IPPS.1996.508145
language
English
LU publication?
yes
id
07e09b27-06af-489d-9230-eec81f625e2d (old id 1785644)
date added to LUP
2011-02-10 10:05:50
date last changed
2016-10-13 05:02:24
@misc{07e09b27-06af-489d-9230-eec81f625e2d,
  abstract     = {A new VLSI architecture for a real-time pipeline FFT processor is proposed. A hardware-oriented radix-22 algorithm is derived by integrating a twiddle factor decomposition technique in the divide-and-conquer approach. The radix-22 algorithm has the same multiplicative complexity as the radix-4 algorithm, but retains the butterfly structure of the radix-2 algorithm. The single-path delay-feedback architecture is used to exploit the spatial regularity in the signal flow graph of the algorithm. For length-N DFT computation, the hardware requirement of the proposed architecture is minimal on both dominant components: log4N-1 complexity multipliers and N-1 complexity data memory. The validity and efficiency of the architecture have been verified by simulation in the hardware description language VHDL.},
  author       = {He, Shousheng and Torkelson, Mats},
  isbn         = {0-8186-7255-2},
  keyword      = {pipeline processing,parallel architectures,parallel algorithms,microprocessor chips,hardware description languages,feedback,fast Fourier transforms,divide and conquer methods,discrete Fourier transforms,delay systems,VLSI,computational complexity,real-time systems},
  language     = {eng},
  pages        = {766--770},
  series       = {[Host publication title missing]},
  title        = {A new approach to pipeline FFT processor},
  url          = {http://dx.doi.org/10.1109/IPPS.1996.508145},
  year         = {1996},
}