Reduced impact of induced gate noise on inductively degenerated LNAs in deep submicron CMOS technologies
(2005) In Analog Integrated Circuits and Signal Processing 42(1). p.31-36- Abstract
- Designers of radio-frequency inductively-degenerated CMOS low-noise-amplifiers have usually not followed the guidelines for achieving minimum noise figure. Nonetheless, state-of-the- art implementations display noise figure values very close to the theoretical minimum. In this paper, we point out that this is due to the effect of the parasitic overlap capacitances in the MOS device. In particular, we show that overlap capacitances lead to a significant induced-gate-noise reduction, especially when deep sub-micron CMOS processes are used.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/1051582
- author
- Rossi, Paolo ; Svelto, Francesco ; Mazzanti, Andrea and Andreani, Pietro LU
- publishing date
- 2005
- type
- Contribution to journal
- publication status
- published
- subject
- in
- Analog Integrated Circuits and Signal Processing
- volume
- 42
- issue
- 1
- pages
- 31 - 36
- publisher
- Springer
- external identifiers
-
- scopus:4544260888
- ISSN
- 0925-1030
- DOI
- 10.1007/s10470-004-6845-z
- language
- English
- LU publication?
- no
- id
- 9c65a1c1-b016-4ed4-afc6-9196ffc3b77c (old id 1051582)
- alternative location
- http://www.springerlink.com/content/fw01u3vva128aeg8/fulltext.pdf
- date added to LUP
- 2016-04-04 09:10:34
- date last changed
- 2022-03-15 18:04:37
@article{9c65a1c1-b016-4ed4-afc6-9196ffc3b77c, abstract = {{Designers of radio-frequency inductively-degenerated CMOS low-noise-amplifiers have usually not followed the guidelines for achieving minimum noise figure. Nonetheless, state-of-the- art implementations display noise figure values very close to the theoretical minimum. In this paper, we point out that this is due to the effect of the parasitic overlap capacitances in the MOS device. In particular, we show that overlap capacitances lead to a significant induced-gate-noise reduction, especially when deep sub-micron CMOS processes are used.}}, author = {{Rossi, Paolo and Svelto, Francesco and Mazzanti, Andrea and Andreani, Pietro}}, issn = {{0925-1030}}, language = {{eng}}, number = {{1}}, pages = {{31--36}}, publisher = {{Springer}}, series = {{Analog Integrated Circuits and Signal Processing}}, title = {{Reduced impact of induced gate noise on inductively degenerated LNAs in deep submicron CMOS technologies}}, url = {{http://dx.doi.org/10.1007/s10470-004-6845-z}}, doi = {{10.1007/s10470-004-6845-z}}, volume = {{42}}, year = {{2005}}, }