A mixed mode design flow for multi GHz ADPLLs
(2011) 29th Norchip conference, 2011- Abstract (Swedish)
- Abstract in Undetermined
A systematic design approach for All Digital Phase Locked Loops (ADPLL) is presented. The whole system excluding Digitally Controlled Oscillator (DCO) and the Time to Digital Converter (TDC) can be synthesized easily in digital design flow. By using standard digital cells, no custom digital cells are needed. All the key problems in synthesis are solved well. The ADPLL is implemented in 90-nm CMOS process technology with the divider-by-two output clock of 2.7GHz. The current consumption is 6.5mA under the power supply of 1.2V.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/2429986
- author
- Shakir, Muhammad ; Abdulaziz, Mohammed LU ; Lu, Ping LU and Andreani, Pietro LU
- organization
- publishing date
- 2011
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- keywords
- all digital phase locked loop, current 2.5 mA, digital cell, digitally controlled oscillator, divider-by-two output clock, frequency 2.7 GHz, mixed mode digital design flow, multiGHz ADPLL, size 90 nm, systematic design approach, time to digital converter, voltage 1.2 V, TDC, DCO, CMOS process technology
- host publication
- [Host publication title missing]
- pages
- 4 pages
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- 29th Norchip conference, 2011
- conference location
- Lund, Sweden
- conference dates
- 2011-11-14 - 2011-11-15
- external identifiers
-
- scopus:84856873811
- ISBN
- 978-1-4577-0514-4
- DOI
- 10.1109/NORCHP.2011.6126714
- language
- English
- LU publication?
- yes
- id
- b4843386-32c1-4e47-a778-5be306af05fb (old id 2429986)
- date added to LUP
- 2016-04-04 10:22:26
- date last changed
- 2022-05-17 02:45:33
@inproceedings{b4843386-32c1-4e47-a778-5be306af05fb, abstract = {{<b>Abstract in Undetermined</b><br/><br> A systematic design approach for All Digital Phase Locked Loops (ADPLL) is presented. The whole system excluding Digitally Controlled Oscillator (DCO) and the Time to Digital Converter (TDC) can be synthesized easily in digital design flow. By using standard digital cells, no custom digital cells are needed. All the key problems in synthesis are solved well. The ADPLL is implemented in 90-nm CMOS process technology with the divider-by-two output clock of 2.7GHz. The current consumption is 6.5mA under the power supply of 1.2V.}}, author = {{Shakir, Muhammad and Abdulaziz, Mohammed and Lu, Ping and Andreani, Pietro}}, booktitle = {{[Host publication title missing]}}, isbn = {{978-1-4577-0514-4}}, keywords = {{all digital phase locked loop; current 2.5 mA; digital cell; digitally controlled oscillator; divider-by-two output clock; frequency 2.7 GHz; mixed mode digital design flow; multiGHz ADPLL; size 90 nm; systematic design approach; time to digital converter; voltage 1.2 V; TDC; DCO; CMOS process technology}}, language = {{eng}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, title = {{A mixed mode design flow for multi GHz ADPLLs}}, url = {{http://dx.doi.org/10.1109/NORCHP.2011.6126714}}, doi = {{10.1109/NORCHP.2011.6126714}}, year = {{2011}}, }