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Asynchronous vs Synchronous SAR ADCs - Performance Beyond Nominal Speed

Karrari, Hamid LU ; Andreani, Pietro LU and Tan, Siyu LU (2024) 19th Conference on Ph.D Research in Microelectronics and Electronics, PRIME 2024 In 2024 19th Conference on Ph.D Research in Microelectronics and Electronics, PRIME 2024
Abstract

This paper presents a comparison between a Itl-bit asynchronous SAR (ASAR) ADC and a 10-bit synchronous SAR (SSAR) ADC, both designed and simulated in a 22-nm FDSOI CMOS process. To further support the simulation results, the ASAR ADC has also been fabricated and measurements are pre-sented. As opposed to the abrupt SNDR collapse in the SSAR ADC, the SNDR of the ASAR ADC shows a more graceful deg-radation as the sampling frequency is increased beyond the highest nominal. At the same time, the ASAR ADC consumes approximately 20% less power than the SSAR ADC.

Please use this url to cite or link to this publication:
author
; and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
asynchronous SAR ADC, CMOS, Successive-approximation ADC (SAR ADC), synchronous SAR ADC
host publication
2024 19th Conference on Ph.D Research in Microelectronics and Electronics, PRIME 2024
series title
2024 19th Conference on Ph.D Research in Microelectronics and Electronics, PRIME 2024
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
conference name
19th Conference on Ph.D Research in Microelectronics and Electronics, PRIME 2024
conference location
Larnaca, Cyprus
conference dates
2024-06-09 - 2024-06-12
external identifiers
  • scopus:85199294887
ISBN
9798350386301
DOI
10.1109/PRIME61930.2024.10559690
language
English
LU publication?
yes
id
3c8478e2-1d0b-4702-928e-ecc39c4d932b
date added to LUP
2024-12-02 11:10:45
date last changed
2025-06-03 01:29:02
@inproceedings{3c8478e2-1d0b-4702-928e-ecc39c4d932b,
  abstract     = {{<p>This paper presents a comparison between a Itl-bit asynchronous SAR (ASAR) ADC and a 10-bit synchronous SAR (SSAR) ADC, both designed and simulated in a 22-nm FDSOI CMOS process. To further support the simulation results, the ASAR ADC has also been fabricated and measurements are pre-sented. As opposed to the abrupt SNDR collapse in the SSAR ADC, the SNDR of the ASAR ADC shows a more graceful deg-radation as the sampling frequency is increased beyond the highest nominal. At the same time, the ASAR ADC consumes approximately 20% less power than the SSAR ADC.</p>}},
  author       = {{Karrari, Hamid and Andreani, Pietro and Tan, Siyu}},
  booktitle    = {{2024 19th Conference on Ph.D Research in Microelectronics and Electronics, PRIME 2024}},
  isbn         = {{9798350386301}},
  keywords     = {{asynchronous SAR ADC; CMOS; Successive-approximation ADC (SAR ADC); synchronous SAR ADC}},
  language     = {{eng}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  series       = {{2024 19th Conference on Ph.D Research in Microelectronics and Electronics, PRIME 2024}},
  title        = {{Asynchronous vs Synchronous SAR ADCs - Performance Beyond Nominal Speed}},
  url          = {{http://dx.doi.org/10.1109/PRIME61930.2024.10559690}},
  doi          = {{10.1109/PRIME61930.2024.10559690}},
  year         = {{2024}},
}