A High-Speed Comparator Using a New Regeneration Latch
(2023) 2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023 p.624-628- Abstract
This paper presents a high-speed comparator which employs a novel regeneration latch to enhance the comparison process. The regeneration stage employs an innovative mechanism that reduces the RC constant at the output while avoiding static power consumption. Furthermore, the proposed comparator is capable of operating seamlessly with a rail-to-rail input common-mode voltage. This is made possible by utilizing two preamplifiers working in parallel. To partially cancel out kickback noise, the proposed comparator also benefits from an intrinsic neutralization technique. The design was simulated in a 22-nm FD-SOI CMOS technology with a supply voltage of 0.8 V showing that the proposed comparator achieves a 17% decrease in delay compared to... (More)
This paper presents a high-speed comparator which employs a novel regeneration latch to enhance the comparison process. The regeneration stage employs an innovative mechanism that reduces the RC constant at the output while avoiding static power consumption. Furthermore, the proposed comparator is capable of operating seamlessly with a rail-to-rail input common-mode voltage. This is made possible by utilizing two preamplifiers working in parallel. To partially cancel out kickback noise, the proposed comparator also benefits from an intrinsic neutralization technique. The design was simulated in a 22-nm FD-SOI CMOS technology with a supply voltage of 0.8 V showing that the proposed comparator achieves a 17% decrease in delay compared to the fastest conventional topology simulated in this paper, while consuming the same amount of power.
(Less)
- author
- Karrari, Hamid LU ; Andreani, Pietro LU and Tan, Siyu LU
- organization
- publishing date
- 2023
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- keywords
- analog-to-digital converter (ADC), high-speed, rail-to-rail, Two-stage comparator
- host publication
- 2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023
- pages
- 5 pages
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- 2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023
- conference location
- Tempe, United States
- conference dates
- 2023-08-06 - 2023-08-09
- external identifiers
-
- scopus:85185371226
- ISBN
- 9798350302103
- DOI
- 10.1109/MWSCAS57524.2023.10405870
- language
- English
- LU publication?
- yes
- id
- 68d34d23-7a61-4f3b-b12c-994f37f224e4
- date added to LUP
- 2024-03-19 11:03:04
- date last changed
- 2024-03-19 11:03:57
@inproceedings{68d34d23-7a61-4f3b-b12c-994f37f224e4, abstract = {{<p>This paper presents a high-speed comparator which employs a novel regeneration latch to enhance the comparison process. The regeneration stage employs an innovative mechanism that reduces the RC constant at the output while avoiding static power consumption. Furthermore, the proposed comparator is capable of operating seamlessly with a rail-to-rail input common-mode voltage. This is made possible by utilizing two preamplifiers working in parallel. To partially cancel out kickback noise, the proposed comparator also benefits from an intrinsic neutralization technique. The design was simulated in a 22-nm FD-SOI CMOS technology with a supply voltage of 0.8 V showing that the proposed comparator achieves a 17% decrease in delay compared to the fastest conventional topology simulated in this paper, while consuming the same amount of power.</p>}}, author = {{Karrari, Hamid and Andreani, Pietro and Tan, Siyu}}, booktitle = {{2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023}}, isbn = {{9798350302103}}, keywords = {{analog-to-digital converter (ADC); high-speed; rail-to-rail; Two-stage comparator}}, language = {{eng}}, pages = {{624--628}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, title = {{A High-Speed Comparator Using a New Regeneration Latch}}, url = {{http://dx.doi.org/10.1109/MWSCAS57524.2023.10405870}}, doi = {{10.1109/MWSCAS57524.2023.10405870}}, year = {{2023}}, }