A 12-bit High-Speed Time-Interleaved Pipelined Asynchronous Successive-Approximation ADC in 22-nm FDSOI CMOS
(2024) In IEEE Access 12. p.44115-44124- Abstract
A 12-bit time-interleaved (TI) analog-to-digital converter (ADC) with pipelined successive-approximation (SAR) channels is presented in this paper. The ADC consists of four TI channels, each incorporating a two-stage pipelined asynchronous SAR ADC. To facilitate clock distribution, a common bootstrapped sampler in front of the four channels is employed. The reset switch in the capacitive digital-to-analog converter (CDAC) of each channel is also bootstrapped to enhance the speed and linearity. A prototype ADC has been designed and implemented in a 22-nm FDSOI CMOS technology, with a core occupation area of 0.43 mm2. Measurements show that the ADC achieves a signal-to-noise-and-distortion ratio of 50dB with a low-frequency input, and of... (More)
A 12-bit time-interleaved (TI) analog-to-digital converter (ADC) with pipelined successive-approximation (SAR) channels is presented in this paper. The ADC consists of four TI channels, each incorporating a two-stage pipelined asynchronous SAR ADC. To facilitate clock distribution, a common bootstrapped sampler in front of the four channels is employed. The reset switch in the capacitive digital-to-analog converter (CDAC) of each channel is also bootstrapped to enhance the speed and linearity. A prototype ADC has been designed and implemented in a 22-nm FDSOI CMOS technology, with a core occupation area of 0.43 mm2. Measurements show that the ADC achieves a signal-to-noise-and-distortion ratio of 50dB with a low-frequency input, and of 48.5 dB at Nyquist. The total power consumption is 37.5 mW; the core ADC consumes 19.3 mW from a 0.8V supply. With a 1.4 GS/s sampling rate and input at Nyquist, the ADC achieves a Walden's figure of merit of 114 fJ/conversion.
(Less)
- author
- Karrari, Hamid LU ; Andreani, Pietro LU and Tan, Siyu LU
- organization
- publishing date
- 2024
- type
- Contribution to journal
- publication status
- published
- subject
- keywords
- Analog-to-digital converter (ADC), asynchronous SAR, bootstrapped switch, CMOS, comparator, dynamic amplifier (DA), pipelined successive approximation (pipelined-SAR), time-interleaved (TI)
- in
- IEEE Access
- volume
- 12
- pages
- 10 pages
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- external identifiers
-
- scopus:85188884248
- ISSN
- 2169-3536
- DOI
- 10.1109/ACCESS.2024.3381037
- language
- English
- LU publication?
- yes
- id
- 7c917782-d56a-4675-ae08-f6226b5306e2
- date added to LUP
- 2024-04-11 11:03:00
- date last changed
- 2024-04-11 11:04:05
@article{7c917782-d56a-4675-ae08-f6226b5306e2, abstract = {{<p>A 12-bit time-interleaved (TI) analog-to-digital converter (ADC) with pipelined successive-approximation (SAR) channels is presented in this paper. The ADC consists of four TI channels, each incorporating a two-stage pipelined asynchronous SAR ADC. To facilitate clock distribution, a common bootstrapped sampler in front of the four channels is employed. The reset switch in the capacitive digital-to-analog converter (CDAC) of each channel is also bootstrapped to enhance the speed and linearity. A prototype ADC has been designed and implemented in a 22-nm FDSOI CMOS technology, with a core occupation area of 0.43 mm2. Measurements show that the ADC achieves a signal-to-noise-and-distortion ratio of 50dB with a low-frequency input, and of 48.5 dB at Nyquist. The total power consumption is 37.5 mW; the core ADC consumes 19.3 mW from a 0.8V supply. With a 1.4 GS/s sampling rate and input at Nyquist, the ADC achieves a Walden's figure of merit of 114 fJ/conversion.</p>}}, author = {{Karrari, Hamid and Andreani, Pietro and Tan, Siyu}}, issn = {{2169-3536}}, keywords = {{Analog-to-digital converter (ADC); asynchronous SAR; bootstrapped switch; CMOS; comparator; dynamic amplifier (DA); pipelined successive approximation (pipelined-SAR); time-interleaved (TI)}}, language = {{eng}}, pages = {{44115--44124}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, series = {{IEEE Access}}, title = {{A 12-bit High-Speed Time-Interleaved Pipelined Asynchronous Successive-Approximation ADC in 22-nm FDSOI CMOS}}, url = {{http://dx.doi.org/10.1109/ACCESS.2024.3381037}}, doi = {{10.1109/ACCESS.2024.3381037}}, volume = {{12}}, year = {{2024}}, }