Energy-Efficient Application-Specific Instruction-Set Processor for Feature Extraction in Smart Vision Systems
(2021) 55th Asilomar Conference on Signals, Systems and Computers, ACSSC 2021 In Conference Record - Asilomar Conference on Signals, Systems and Computers 2021-October. p.324-328- Abstract
Smart vision sensor systems enable many computer vision applications such as autonomous drones and wearable devices. These battery-powered gadgets have very stringent power consumption requirements. Close-to-sensor feature extraction compressing the full image into descriptive keypoints, is crucial as it allows for several design optimizations. First, the amount of necessary on-chip memory can be lessened. Second, the volume of data that needs to be exchanged between nodes in Internet of Things (IoT) applications can also be reduced. This work explores the usage of an Application Specific Instruction Set Processor (ASIP) tailored to perform energy-efficient feature extraction in real-time. The ASIP features a Very Long Instruction Word... (More)
Smart vision sensor systems enable many computer vision applications such as autonomous drones and wearable devices. These battery-powered gadgets have very stringent power consumption requirements. Close-to-sensor feature extraction compressing the full image into descriptive keypoints, is crucial as it allows for several design optimizations. First, the amount of necessary on-chip memory can be lessened. Second, the volume of data that needs to be exchanged between nodes in Internet of Things (IoT) applications can also be reduced. This work explores the usage of an Application Specific Instruction Set Processor (ASIP) tailored to perform energy-efficient feature extraction in real-time. The ASIP features a Very Long Instruction Word (VLIW) central core comprising one RV32I RISCV and three vector slots. The on-chip memory sub-system implements parallel multi-bank memories with near-memory data shuffling to enable single-cycle multi-pattern vector access. As a case study, Oriented FAST and Rotated BRIEF (ORB) is used to evaluate the proposed architecture. We show that the architecture supports VGA-resolution images at 140 Frames-Per-Second (FPS), for one scale, reducing the number of memory accesses by 2 orders of magnitude comparing to other embedded general-purpose architectures.
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- author
- Ferreira, Lucas LU ; Malkowsky, Steffen LU ; Persson, Patrik LU ; Karlsson, Sven ; Astrom, Karl LU and Liu, Liang LU
- organization
- publishing date
- 2021
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- keywords
- ASIP, Feature Extraction, ORB, vision-based Simultaneous Localization And Mapping (SLAM)
- host publication
- Conference Record - Asilomar Conference on Signals, Systems and Computers
- series title
- Conference Record - Asilomar Conference on Signals, Systems and Computers
- editor
- Matthews, Michael B.
- volume
- 2021-October
- pages
- 5 pages
- publisher
- IEEE Computer Society
- conference name
- 55th Asilomar Conference on Signals, Systems and Computers, ACSSC 2021
- conference location
- Virtual, Pacific Grove, United States
- conference dates
- 2021-10-31 - 2021-11-03
- external identifiers
-
- scopus:85127036785
- ISSN
- 1058-6393
- ISBN
- 9781665458283
- DOI
- 10.1109/IEEECONF53345.2021.9723114
- language
- English
- LU publication?
- yes
- id
- 8e248c9d-b893-4cef-aef4-3a3f700a9bd4
- date added to LUP
- 2022-05-16 11:57:22
- date last changed
- 2024-03-29 08:21:28
@inproceedings{8e248c9d-b893-4cef-aef4-3a3f700a9bd4, abstract = {{<p>Smart vision sensor systems enable many computer vision applications such as autonomous drones and wearable devices. These battery-powered gadgets have very stringent power consumption requirements. Close-to-sensor feature extraction compressing the full image into descriptive keypoints, is crucial as it allows for several design optimizations. First, the amount of necessary on-chip memory can be lessened. Second, the volume of data that needs to be exchanged between nodes in Internet of Things (IoT) applications can also be reduced. This work explores the usage of an Application Specific Instruction Set Processor (ASIP) tailored to perform energy-efficient feature extraction in real-time. The ASIP features a Very Long Instruction Word (VLIW) central core comprising one RV32I RISCV and three vector slots. The on-chip memory sub-system implements parallel multi-bank memories with near-memory data shuffling to enable single-cycle multi-pattern vector access. As a case study, Oriented FAST and Rotated BRIEF (ORB) is used to evaluate the proposed architecture. We show that the architecture supports VGA-resolution images at 140 Frames-Per-Second (FPS), for one scale, reducing the number of memory accesses by 2 orders of magnitude comparing to other embedded general-purpose architectures. </p>}}, author = {{Ferreira, Lucas and Malkowsky, Steffen and Persson, Patrik and Karlsson, Sven and Astrom, Karl and Liu, Liang}}, booktitle = {{Conference Record - Asilomar Conference on Signals, Systems and Computers}}, editor = {{Matthews, Michael B.}}, isbn = {{9781665458283}}, issn = {{1058-6393}}, keywords = {{ASIP; Feature Extraction; ORB; vision-based Simultaneous Localization And Mapping (SLAM)}}, language = {{eng}}, pages = {{324--328}}, publisher = {{IEEE Computer Society}}, series = {{Conference Record - Asilomar Conference on Signals, Systems and Computers}}, title = {{Energy-Efficient Application-Specific Instruction-Set Processor for Feature Extraction in Smart Vision Systems}}, url = {{http://dx.doi.org/10.1109/IEEECONF53345.2021.9723114}}, doi = {{10.1109/IEEECONF53345.2021.9723114}}, volume = {{2021-October}}, year = {{2021}}, }