Low-temperature back-end-of-line technology compatible with III-V nanowire MOSFETs
(2019) In Journal of Vacuum Science and Technology B: Nanotechnology and Microelectronics 37(6).- Abstract
We present a low-temperature processing scheme for the integration of either lateral or vertical nanowire (NW) transistors with a multilayer back-end-of-line interconnect stack. The nanowire device temperature budget has been addressed, and materials for the interconnect fabrication have been selected accordingly. A benzocyclobutene (BCB) polymer is used as an interlayer dielectric, with interconnect vias formed by reactive ion etching. A study on via etching conditions for multiple interlayer dielectric thicknesses reveals that the sidewall slope can be engineered. An optimal reactive ion etch is identified at 250 mTorr chamber pressure and power of 160 W, using an SF6 to O2 gas mix of 4%. This results in a low... (More)
We present a low-temperature processing scheme for the integration of either lateral or vertical nanowire (NW) transistors with a multilayer back-end-of-line interconnect stack. The nanowire device temperature budget has been addressed, and materials for the interconnect fabrication have been selected accordingly. A benzocyclobutene (BCB) polymer is used as an interlayer dielectric, with interconnect vias formed by reactive ion etching. A study on via etching conditions for multiple interlayer dielectric thicknesses reveals that the sidewall slope can be engineered. An optimal reactive ion etch is identified at 250 mTorr chamber pressure and power of 160 W, using an SF6 to O2 gas mix of 4%. This results in a low via resistance, even for scaled structures. The BCB dielectric etch rate and dielectric-to-soft mask etch selectivity are quantified. Electrical measurements on lateral and vertical III-V NW transistors, before and after the back-end-of-line process, are presented. No performance degradation is observed, only minor differences that are attributed to contact annealing and threshold voltage shift.
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- author
- Andric, Stefan LU ; Ohlsson Fhager, Lars LU ; Lindelöw, Fredrik LU ; Kilpi, Olli Pekka LU and Wernersson, Lars Erik LU
- organization
- publishing date
- 2019-10-17
- type
- Contribution to journal
- publication status
- published
- subject
- in
- Journal of Vacuum Science and Technology B: Nanotechnology and Microelectronics
- volume
- 37
- issue
- 6
- article number
- 061204
- publisher
- AVS Science and Technology Society
- external identifiers
-
- scopus:85073801819
- ISSN
- 2166-2746
- DOI
- 10.1116/1.5121017
- language
- English
- LU publication?
- yes
- id
- b2fab2f5-7c97-4b67-b638-b94da3864981
- date added to LUP
- 2019-10-29 14:40:50
- date last changed
- 2023-10-21 22:32:00
@article{b2fab2f5-7c97-4b67-b638-b94da3864981, abstract = {{<p>We present a low-temperature processing scheme for the integration of either lateral or vertical nanowire (NW) transistors with a multilayer back-end-of-line interconnect stack. The nanowire device temperature budget has been addressed, and materials for the interconnect fabrication have been selected accordingly. A benzocyclobutene (BCB) polymer is used as an interlayer dielectric, with interconnect vias formed by reactive ion etching. A study on via etching conditions for multiple interlayer dielectric thicknesses reveals that the sidewall slope can be engineered. An optimal reactive ion etch is identified at 250 mTorr chamber pressure and power of 160 W, using an SF<sub>6</sub> to O<sub>2</sub> gas mix of 4%. This results in a low via resistance, even for scaled structures. The BCB dielectric etch rate and dielectric-to-soft mask etch selectivity are quantified. Electrical measurements on lateral and vertical III-V NW transistors, before and after the back-end-of-line process, are presented. No performance degradation is observed, only minor differences that are attributed to contact annealing and threshold voltage shift.</p>}}, author = {{Andric, Stefan and Ohlsson Fhager, Lars and Lindelöw, Fredrik and Kilpi, Olli Pekka and Wernersson, Lars Erik}}, issn = {{2166-2746}}, language = {{eng}}, month = {{10}}, number = {{6}}, publisher = {{AVS Science and Technology Society}}, series = {{Journal of Vacuum Science and Technology B: Nanotechnology and Microelectronics}}, title = {{Low-temperature back-end-of-line technology compatible with III-V nanowire MOSFETs}}, url = {{http://dx.doi.org/10.1116/1.5121017}}, doi = {{10.1116/1.5121017}}, volume = {{37}}, year = {{2019}}, }