Breeta Sengupta (Former)
11 – 16 of 16
- show: 10
- |
- sort: year (new to old)
Close
Embed this list
<iframe src=""
width=""
height=""
allowtransparency="true"
frameborder="0">
</iframe>
- « previous
- 1
- 2
- next »
- 2011
-
Mark
Test Scheduling for 3D Stacked ICs under Power Constraints
Sengupta, Breeta LU ; Ingelsson, Urban and Larsson, Erik LU
(2011)
2nd IEEE International Workshop on Reliability Aware System Design and Test (RASDAT)
- Contribution to conference › Paper, not in proceeding
-
Mark
Test Planning for 3D Stacked ICs with Through-Silicon Vias
Sengupta, Breeta LU ; Ingelsson, Urban and Larsson, Erik LU
(2011)
Second IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits
- Contribution to conference › Paper, not in proceeding
-
Mark
Test Cost Modeling for 3D Stacked Chips with Through-Silicon Vias
Sengupta, Breeta LU ; Ingelsson, Urban and Larsson, Erik LU
(2011)
Swedish System-on-Chip Conference, SSoCC 2011
- Contribution to conference › Paper, not in proceeding
-
Mark
Test Scheduling and Test Access Optimization for Core-Based 3D Stacked ICs with Through-Silicon Vias: poster
Sengupta, Breeta LU ; Ingelsson, Urban and Larsson, Erik LU
(2011)
IEEE European Test Symposium (ETS), 2011
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2010
-
Mark
Scheduling Tests for Stacked 3D Chips under Power Constraints
- Contribution to conference › Paper, not in proceeding
-
Mark
Power Constrained Test Scheduling for 3D Stacked Chips: poster
Sengupta, Breeta LU ; Ingelsson, Urban and Larsson, Erik LU
(2010)
1st IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits
- Contribution to conference › Poster
- « previous
- 1
- 2
- next »