Erik Larsson
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- 2009
-
Mark
Power Efficient Redundant Execution for Chip Multiprocessors
- Contribution to conference › Paper, not in proceeding
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Mark
Generation of Minimal Leakage Input Vectors with Constrained NBTI Degradation
- Contribution to conference › Paper, not in proceeding
-
Mark
On Scan Chain Diagnosis for Intermittent Faults
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Capture Power Reduction for Modular System-on-Chip Test
(2009) IEEE/VSI VLSI Design and Test Symposium (VDAT)
- Contribution to conference › Paper, not in proceeding
- 2008
-
Mark
Cycle-Accurate Test Power Modeling and its Application to SoC Test Architecture Design and Scheduling
(2008) In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27(5). p.973-977
- Contribution to journal › Article
-
Mark
An Architecture for Integrated Test Data Compression and Abort-on-Fail Testing in a Multi-Site Environment
- Contribution to journal › Article
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Mark
A reconfigurable power conscious core wrapper and its application to system-on-chip test scheduling
- Contribution to journal › Article
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Mark
Core-Level Expansion of Compressed Test Patterns
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
SOC Test Optimization with Compression-Technique Selection
(2008) A Workshop in Conjunction with the International Test Conference
- Contribution to conference › Paper, not in proceeding
-
Mark
On Reduction of Capture Power for Modular System-on-Chip Test
(2008) IEEE Workshop on RTL and High Level Testing WRTLT08
- Contribution to conference › Paper, not in proceeding
