Erik Larsson
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- 2011
-
Mark
Test Scheduling and Test Access Optimization for Core-Based 3D Stacked ICs with Through-Silicon Vias: poster
(2011) IEEE European Test Symposium (ETS), 2011
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2010
-
Mark
Estimating Error-Probability and Its Application for Optimizing Roll-back Recovery with Checkpointing
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Test scheduling on IJTAG
(2010) Nordic Test Forum (NTF 2010),
- Contribution to conference › Paper, not in proceeding
-
Mark
Scan Cells Reordering to Minimize Peak Power During Test Cycle : A Graph Theoretic Approach
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Study on Combined Test-Data Compression and Test Planning for Testing of Modular SoCs
(2010)
- Chapter in Book/Report/Conference proceeding › Book chapter
-
Mark
A Distributed Architecture to Check Global Properties for Post-Silicon Debug
(2010) IEEE European Test Symposium (ETS'10), 2010
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Optimizing Fault Tolerance for Multi-Processor System-on-Chip
(2010)
- Chapter in Book/Report/Conference proceeding › Book chapter
-
Mark
Test Scheduling of Modular System-on-Chip under Capture Power Constraint
(2010) IEEE Eleventh Workshop on RTL and High Level Testing, 2010
- Contribution to conference › Paper, not in proceeding
-
Mark
Checking Pipelined Distributed and Global Properties at Post-silicon Debug
(2010) DAC Workshop on Diagnostic Services in Network-on-Chips (DSNoC'10)
- Contribution to conference › Paper, not in proceeding
-
Mark
Efficient Embedding of Deterministic Test Data
(2010) 19th IEEE Asian Test Symposium (ATS10)
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
