Erik Larsson
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- 2010
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Mark
Thermal Aware Test Scheduling for Stacked Multi-Chip-Modules
(2010) IEEE East-West Design and Test Symposium (EWDTS10)
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Graph Theoretic Approach for Scan Cell Reordering to Minimize Peak Shift Power
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Energy-Efficient Redundant Execution for Chip Multiprocessors
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Test Time Analysis for IEEE P1687
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Scheduling Tests for Stacked 3D Chips under Power Constraints
(2010) Swedish SoC Conference 2010
- Contribution to conference › Paper, not in proceeding
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Mark
Mapping and Scheduling of Jobs in Homogeneous NoC-based MPSoC
(2010) Swedish SoC Conference 2010
- Contribution to conference › Paper, not in proceeding
-
Mark
Test Scheduling of Modular System-on-Chip under Capture Power Constraint
(2010) IEEE Eleventh Workshop on RTL and High Level Testing, 2010
- Contribution to conference › Paper, not in proceeding
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Mark
Checking Pipelined Distributed and Global Properties at Post-silicon Debug
(2010) DAC Workshop on Diagnostic Services in Network-on-Chips (DSNoC'10)
- Contribution to conference › Paper, not in proceeding
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Mark
Efficient Embedding of Deterministic Test Data
(2010) Swedish SoC Conference 2010
- Contribution to conference › Paper, not in proceeding
-
Mark
Test scheduling on IJTAG
(2010) Nordic Test Forum (NTF 2010),
- Contribution to conference › Paper, not in proceeding
