Erik Larsson
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- 2002
-
Mark
An Integrated Framework for the Design and Optimization of SOC Test Solutions
2002) p.21-36(
- Chapter in Book/Report/Conference proceeding › Book chapter
- 2001
-
Mark
The Design and Optimization of SOC Test Solutions
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
An Integrated System-On-Chip Test Framework
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
System-on-Chip Test Parallelization Under Power Constraints
2001)(
- Other contribution › Miscellaneous
-
Mark
Test Scheduling and Scan-Chain Division Under Power Constraint
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2000
-
Mark
An Integrated System-Level Design for Testability Methodology An Integrated System-Level Design for Testability Methodology
2000)(
- Thesis › Doctoral thesis (monograph)
-
Mark
A Technique for Test Infrastructure Design and Test Scheduling
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
System-on-Chip Test Bus Design and Test Scheduling
2000) International Test Synthesis Workshop,2000(
- Contribution to conference › Paper, not in proceeding
-
Mark
Test Infrastructure Design and Test Scheduling Optimization
2000)(
- Other contribution › Miscellaneous