Ping Lu (Former)
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- 2013
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Mark
A 2-D GRO Vernier Time-to-Digital Converter with Large Input Range and Small Latency
(
- Contribution to journal › Article
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Mark
A Wide Bandwidth Fractional-N Synthesizer for LTE with Phase Noise Cancellation Using a Hybrid- -DAC and Charge Re-timing
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A 2-D GRO Vernier Time-to-Digital Converter with Large Input Range and Small Latency
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 90nm CMOS Gated-Ring-Oscillator-Based 2-Dimension Vernier Time-to-Digital Converter
2013) Norchip conference, 2012(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2012
-
Mark
A 90nm CMOS Digital PLL Based on Vernier-Gated-Ring-Oscillator Time-to-Digital Converter
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A 3.6mW, 90nm CMOS Gated-Vernier Time-to-Digital Converter with an Equivalent Resolution of 3.2ps
(
- Contribution to journal › Article
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Mark
A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS
2012) GigaHertz Symposium 2012(
- Contribution to conference › Abstract
- 2011
-
Mark
A 5GHz 90-nm CMOS all digital phase-locked loop
(
- Contribution to journal › Article
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Mark
A mixed mode design flow for multi GHz ADPLLs
2011) 29th Norchip conference, 2011(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A 90nm CMOS Gated-Ring-Oscillator-Based Vernier Time-to-Digital Converter with Improved Resolution
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding