Pietro Andreani
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- 2013
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Mark
A 90nm CMOS Gated-Ring-Oscillator-Based 2-Dimension Vernier Time-to-Digital Converter
2013) Norchip conference, 2012(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A Push-Pull Class-C CMOS VCO
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- Contribution to journal › Article
- 2012
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Mark
Introduction to the Special Issue on the 2012 IEEE International Solid-State Circuits Conference
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- Contribution to journal › Debate/Note/Editorial
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Mark
A Continuous Time Delta-Sigma Modulator with Reduced Clock Jitter Sensitivity through DSCR Feedback
2012) In Analog Integrated Circuits and Signal Processing(
- Contribution to journal › Article
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Mark
A 90nm CMOS Digital PLL Based on Vernier-Gated-Ring-Oscillator Time-to-Digital Converter
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
An Analysis of 1/f Noise to Phase Noise Conversion in CMOS Harmonic Oscillators
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- Contribution to journal › Article
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Mark
Phase Noise Analysis of the Tuned-Input-Tuned-Output (TITO) Oscillator
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- Contribution to journal › Article
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Mark
Harmonic Rejection Mixer at ADC Input for Complex IF Dual Carrier Receiver Architecture
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- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A 7.5 mW 9 MHz CT Delta-Sigma Modulator in 65 nm CMOS with 69 dB SNDR and Reduced Sensitivity to Loop Delay Variations
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- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A 3.6mW, 90nm CMOS Gated-Vernier Time-to-Digital Converter with an Equivalent Resolution of 3.2ps
(
- Contribution to journal › Article