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Power Reduction in Custom CMOS Digital Filter Structures

Åström, Pontus LU ; Nilsson, Peter LU and Torkelson, Mats LU (1999) In Analog Integrated Circuits and Signal Processing 18(1). p.97-105
Abstract
Today the main optimization parameter of digital filters is the filter order. By the aid of two implemented filters we will show that both power and speed can be enhanced if the optimization effort is made on reducing the filter coefficient lengths rather than minimizing the order. Both filters have been designed from the same specification, one as a standard minimum order filter, the other as a filter with short coefficients found by a computer search. The minimum order filter is of order three with seven bits long coefficients. The coefficient optimized filter is of order six with two bits long coefficients. Both filters were implemented with bit-serial fixed coefficient arithmetic in two's complement representation in a 0.8µ, two metal... (More)
Today the main optimization parameter of digital filters is the filter order. By the aid of two implemented filters we will show that both power and speed can be enhanced if the optimization effort is made on reducing the filter coefficient lengths rather than minimizing the order. Both filters have been designed from the same specification, one as a standard minimum order filter, the other as a filter with short coefficients found by a computer search. The minimum order filter is of order three with seven bits long coefficients. The coefficient optimized filter is of order six with two bits long coefficients. Both filters were implemented with bit-serial fixed coefficient arithmetic in two's complement representation in a 0.8µ, two metal layers CMOS process. Measurements show an eightfold speedup at half the power consumption and only 30% area cost for the coefficient optimized filter. (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Contribution to journal
publication status
published
subject
keywords
full custom design, lattice wave digital structure, digital filter, low power, coefficient optimization, baseband filter
in
Analog Integrated Circuits and Signal Processing
volume
18
issue
1
pages
97 - 105
publisher
Springer
external identifiers
  • scopus:0032632183
ISSN
0925-1030
DOI
10.1023/A:1008311805609
language
English
LU publication?
yes
id
979a0893-cafa-4322-8e4b-71f8c0118563 (old id 1033978)
date added to LUP
2008-02-22 14:01:29
date last changed
2017-01-01 06:54:54
@article{979a0893-cafa-4322-8e4b-71f8c0118563,
  abstract     = {Today the main optimization parameter of digital filters is the filter order. By the aid of two implemented filters we will show that both power and speed can be enhanced if the optimization effort is made on reducing the filter coefficient lengths rather than minimizing the order. Both filters have been designed from the same specification, one as a standard minimum order filter, the other as a filter with short coefficients found by a computer search. The minimum order filter is of order three with seven bits long coefficients. The coefficient optimized filter is of order six with two bits long coefficients. Both filters were implemented with bit-serial fixed coefficient arithmetic in two's complement representation in a 0.8µ, two metal layers CMOS process. Measurements show an eightfold speedup at half the power consumption and only 30% area cost for the coefficient optimized filter.},
  author       = {Åström, Pontus and Nilsson, Peter and Torkelson, Mats},
  issn         = {0925-1030},
  keyword      = {full custom design,lattice wave digital structure,digital filter,low power,coefficient optimization,baseband filter},
  language     = {eng},
  number       = {1},
  pages        = {97--105},
  publisher    = {Springer},
  series       = {Analog Integrated Circuits and Signal Processing},
  title        = {Power Reduction in Custom CMOS Digital Filter Structures},
  url          = {http://dx.doi.org/10.1023/A:1008311805609},
  volume       = {18},
  year         = {1999},
}