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Vertical enhancement-mode InAs nanowire field-effect transistor with 50-nm wrap gate

Thelander, Claes LU ; Fröberg, Linus LU ; Rehnstedt, Carl LU ; Samuelson, Lars LU and Wernersson, Lars-Erik LU (2008) In IEEE Electron Device Letters 29(3). p.206-208
Abstract
We present results on fabrication and de characterization of vertical InAs nanowire wrap-gate field-effect transistor arrays with a gate length of 50 nm. The wrap gate is defined by evaporation of 50-nm Cr onto a 10-nm-thick HfO2 gate dielectric, where the gate is also separated from the source contact with a 100-nm SiOx spacer layer. For a drain voltage of 0.5 V, we observe a normalized transconductance of 0.5 S/mm, a subthreshold slope around 90 mV/dec, and a threshold voltage just above 0 V. The highest observed normalized on current is 0.2 A/mm, with an off current of 0.2 mA/mm. These devices show a considerable improvement compared to previously reported vertical InAs devices with SiNx gate dielectrics.
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author
organization
publishing date
type
Contribution to journal
publication status
published
subject
keywords
field-effect transistor (FET), InAs, nanowires
in
IEEE Electron Device Letters
volume
29
issue
3
pages
206 - 208
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • wos:000253441900001
  • scopus:40749151146
ISSN
0741-3106
DOI
10.1109/LED.2007.915374
language
English
LU publication?
yes
id
3f3f21d8-17b8-47d3-8039-f41b324a9c9b (old id 1193802)
date added to LUP
2008-09-09 18:35:29
date last changed
2017-10-22 04:26:27
@article{3f3f21d8-17b8-47d3-8039-f41b324a9c9b,
  abstract     = {We present results on fabrication and de characterization of vertical InAs nanowire wrap-gate field-effect transistor arrays with a gate length of 50 nm. The wrap gate is defined by evaporation of 50-nm Cr onto a 10-nm-thick HfO2 gate dielectric, where the gate is also separated from the source contact with a 100-nm SiOx spacer layer. For a drain voltage of 0.5 V, we observe a normalized transconductance of 0.5 S/mm, a subthreshold slope around 90 mV/dec, and a threshold voltage just above 0 V. The highest observed normalized on current is 0.2 A/mm, with an off current of 0.2 mA/mm. These devices show a considerable improvement compared to previously reported vertical InAs devices with SiNx gate dielectrics.},
  author       = {Thelander, Claes and Fröberg, Linus and Rehnstedt, Carl and Samuelson, Lars and Wernersson, Lars-Erik},
  issn         = {0741-3106},
  keyword      = {field-effect transistor (FET),InAs,nanowires},
  language     = {eng},
  number       = {3},
  pages        = {206--208},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  series       = {IEEE Electron Device Letters},
  title        = {Vertical enhancement-mode InAs nanowire field-effect transistor with 50-nm wrap gate},
  url          = {http://dx.doi.org/10.1109/LED.2007.915374},
  volume       = {29},
  year         = {2008},
}