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Vertical InAs Nanowire Wrap Gate Transistors on Si Substrates

Rehnstedt, Carl LU ; Mårtensson, Thomas LU ; Thelander, Claes LU ; Samuelson, Lars LU and Wernersson, Lars-Erik LU (2008) In IEEE Transactions on Electron Devices 55(11). p.3037-3041
Abstract
We report on InAs enhancement-mode field-effect transistors integrated directly on Si substrates. The transistors consist of vertical InAs nanowires, grown on Si substrates without the use of metal seed particles, and they are processed with a 50-nm-long metal wrap gate and high-kappa gate dielectric. Device characteristics showing enhancement-mode operation are reported. The output characteristics are asymmetric due to the band alignment and band bending at the InAs/Si interface. The implemented transistor geometry can therefore also serve as a test structure for investigating the InAs/Si heterointerface. From temperature-dependent measurements, we deduce an activation energy of about 200 meV for the TnAs/Si conduction band offset.
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author
organization
publishing date
type
Contribution to journal
publication status
published
subject
keywords
nanowires (NWs), Field-effect transistor (FET), InAs, on Si, III-V, wrap gate
in
IEEE Transactions on Electron Devices
volume
55
issue
11
pages
3037 - 3041
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • wos:000260899000022
  • scopus:56549116060
ISSN
0018-9383
DOI
10.1109/TED.2008.2005179
language
English
LU publication?
yes
id
f1625233-b029-4c26-9308-cb6e36ba32a2 (old id 1283438)
date added to LUP
2009-02-10 11:40:01
date last changed
2017-10-01 04:05:36
@article{f1625233-b029-4c26-9308-cb6e36ba32a2,
  abstract     = {We report on InAs enhancement-mode field-effect transistors integrated directly on Si substrates. The transistors consist of vertical InAs nanowires, grown on Si substrates without the use of metal seed particles, and they are processed with a 50-nm-long metal wrap gate and high-kappa gate dielectric. Device characteristics showing enhancement-mode operation are reported. The output characteristics are asymmetric due to the band alignment and band bending at the InAs/Si interface. The implemented transistor geometry can therefore also serve as a test structure for investigating the InAs/Si heterointerface. From temperature-dependent measurements, we deduce an activation energy of about 200 meV for the TnAs/Si conduction band offset.},
  author       = {Rehnstedt, Carl and Mårtensson, Thomas and Thelander, Claes and Samuelson, Lars and Wernersson, Lars-Erik},
  issn         = {0018-9383},
  keyword      = {nanowires (NWs),Field-effect transistor (FET),InAs,on Si,III-V,wrap gate},
  language     = {eng},
  number       = {11},
  pages        = {3037--3041},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  series       = {IEEE Transactions on Electron Devices},
  title        = {Vertical InAs Nanowire Wrap Gate Transistors on Si Substrates},
  url          = {http://dx.doi.org/10.1109/TED.2008.2005179},
  volume       = {55},
  year         = {2008},
}