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Vertical III-V Nanowires For In-Memory Computing

Mamidala, Saketh Ram LU orcid (2023)
Abstract
In recent times, deep neural networks (DNNs) have demonstrated great potential in various machine learning applications,
such as image classification and object detection for autonomous driving. However, increasing the accuracy of DNNs
requires scaled, faster, and more energy-efficient hardware, which is limited by the von Neumann architecture where
separate memory and computing units lead to a bottleneck in performance. A promising solution to address the von
Neumann bottleneck is in-memory computing, which can be achieved by integrating non-volatile memory cells such as
RRAMs into dense crossbar arrays. On the hardware side, the 1-transistor-1-resistor (1T1R) configuration has been central
to numerous... (More)
In recent times, deep neural networks (DNNs) have demonstrated great potential in various machine learning applications,
such as image classification and object detection for autonomous driving. However, increasing the accuracy of DNNs
requires scaled, faster, and more energy-efficient hardware, which is limited by the von Neumann architecture where
separate memory and computing units lead to a bottleneck in performance. A promising solution to address the von
Neumann bottleneck is in-memory computing, which can be achieved by integrating non-volatile memory cells such as
RRAMs into dense crossbar arrays. On the hardware side, the 1-transistor-1-resistor (1T1R) configuration has been central
to numerous demonstrations of reservoir, in-memory and neuromorphic computing.

In this thesis, to achieve a 1T1R cell with a minimal footprint of 4F2, a technology platform has been developed to integrate a
vertical nanowire GAA MOSFET as a selector device for the RRAM. Firstly, the effect of the geometry (planar to vertical) of
the ITO/HfO2/TiN RRAM cell was studied where low energy switching (0.49 pJ) and high endurance (106) were achieved
in the vertical configuration. Furthermore, InAs was incorporated as the GAA MOSFET selector channel material to
leverage the beneficial transport properties of III-V materials desirable for supply voltage scaling. Finally, an approach was
developed wherein InAs is used as the selector channel as well as the RRAM electrode by carefully tuning the InAs native
oxides. This thesis also presents low-frequency noise characterization of the RRAM cell as well as the MOSFET to further
understand the semiconductor/oxide interface. The vertical 1T1R cell developed in this thesis enables the implementation
of Boolean logic operations using a single vertical nanowire while reducing the footprint by 51x when compared to its
traditional CMOS counterpart. (Less)
Please use this url to cite or link to this publication:
author
supervisor
opponent
  • Prof. Ielmini, Daniele, Politecnico di Milano, Italy.
organization
publishing date
type
Thesis
publication status
published
subject
keywords
RRAM, 1T1R, gate all-around, MOSFET, III-V nanowire, In-memory computing
publisher
Department of Electrical and Information Technology, Lund University
defense location
Lecture Hall E:B, building E, Ole Römers väg 3, Faculty of Engineering LTH, Lund University, Lund. The dissertation will be live streamed, but part of the premises is to be excluded from the live stream.
defense date
2023-09-01 09:15:00
ISBN
978-91-8039-749-0
978-91-8039-750-6
language
English
LU publication?
yes
id
1bb1fdef-85b9-4050-931c-7fe07801b13f
date added to LUP
2023-06-11 23:00:09
date last changed
2023-06-13 10:03:22
@phdthesis{1bb1fdef-85b9-4050-931c-7fe07801b13f,
  abstract     = {{In recent times, deep neural networks (DNNs) have demonstrated great potential in various machine learning applications,<br/>such as image classification and object detection for autonomous driving. However, increasing the accuracy of DNNs<br/>requires scaled, faster, and more energy-efficient hardware, which is limited by the von Neumann architecture where<br/>separate memory and computing units lead to a bottleneck in performance. A promising solution to address the von<br/>Neumann bottleneck is in-memory computing, which can be achieved by integrating non-volatile memory cells such as<br/>RRAMs into dense crossbar arrays. On the hardware side, the 1-transistor-1-resistor (1T1R) configuration has been central<br/>to numerous demonstrations of reservoir, in-memory and neuromorphic computing.<br/><br/>In this thesis, to achieve a 1T1R cell with a minimal footprint of 4F<sup>2</sup>, a technology platform has been developed to integrate a<br/>vertical nanowire GAA MOSFET as a selector device for the RRAM. Firstly, the effect of the geometry (planar to vertical) of<br/>the ITO/HfO<sub>2</sub>/TiN RRAM cell was studied where low energy switching (0.49 pJ) and high endurance (10<sup>6</sup>) were achieved<br/>in the vertical configuration. Furthermore, InAs was incorporated as the GAA MOSFET selector channel material to<br/>leverage the beneficial transport properties of III-V materials desirable for supply voltage scaling. Finally, an approach was<br/>developed wherein InAs is used as the selector channel as well as the RRAM electrode by carefully tuning the InAs native<br/>oxides. This thesis also presents low-frequency noise characterization of the RRAM cell as well as the MOSFET to further<br/>understand the semiconductor/oxide interface. The vertical 1T1R cell developed in this thesis enables the implementation<br/>of Boolean logic operations using a single vertical nanowire while reducing the footprint by 51x when compared to its<br/>traditional CMOS counterpart.}},
  author       = {{Mamidala, Saketh Ram}},
  isbn         = {{978-91-8039-749-0}},
  keywords     = {{RRAM; 1T1R; gate all-around; MOSFET; III-V nanowire; In-memory computing}},
  language     = {{eng}},
  month        = {{06}},
  publisher    = {{Department of Electrical and Information Technology, Lund University}},
  school       = {{Lund University}},
  title        = {{Vertical III-V Nanowires For In-Memory Computing}},
  url          = {{https://lup.lub.lu.se/search/files/150300508/Thesis_SakethRamMamidala.pdf}},
  year         = {{2023}},
}