Properties of III-V nanowires : MOSFETs and TunnelFETs
(2017) 2017 Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 p.99-100- Abstract
This paper describes the properties and performance status of vertical III-V nanowire transistors. The development of key process modules has advanced the vertical fabrication technology and competitive device performance is reported for InAs MOSFETs and TunnelFETs. Besides the benefits in electrostatic control and the ease in integration on Si substrates, the vertical transistors offers a path towards 3D device integration as demonstrated by the stacked track-and-hold circuit where a capacitor is integrated on top of the vertical transistor for area reduction.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/22571e13-3272-4922-9de4-1d0e592ab84f
- author
- Wernersson, Lars-Erik LU
- organization
- publishing date
- 2017-07-01
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- keywords
- III-V MOSFETs, III-V nanowires, InAs, InAs//GaSb, TFETs
- host publication
- Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings
- issue
- INSPEC Accession Number: 16998248
- article number
- 7962611
- pages
- 2 pages
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- 2017 Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017
- conference location
- Athens, Greece
- conference dates
- 2017-04-03 - 2017-04-05
- external identifiers
-
- scopus:85026749104
- ISSN
- 2472-9132
- ISBN
- 9781509053131
- DOI
- 10.1109/ULIS.2017.7962611
- language
- English
- LU publication?
- yes
- id
- 22571e13-3272-4922-9de4-1d0e592ab84f
- date added to LUP
- 2017-08-31 15:57:54
- date last changed
- 2022-02-14 21:38:20
@inproceedings{22571e13-3272-4922-9de4-1d0e592ab84f, abstract = {{<p>This paper describes the properties and performance status of vertical III-V nanowire transistors. The development of key process modules has advanced the vertical fabrication technology and competitive device performance is reported for InAs MOSFETs and TunnelFETs. Besides the benefits in electrostatic control and the ease in integration on Si substrates, the vertical transistors offers a path towards 3D device integration as demonstrated by the stacked track-and-hold circuit where a capacitor is integrated on top of the vertical transistor for area reduction.</p>}}, author = {{Wernersson, Lars-Erik}}, booktitle = {{Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings}}, isbn = {{9781509053131}}, issn = {{2472-9132}}, keywords = {{III-V MOSFETs; III-V nanowires; InAs; InAs//GaSb; TFETs}}, language = {{eng}}, month = {{07}}, number = {{INSPEC Accession Number: 16998248}}, pages = {{99--100}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, title = {{Properties of III-V nanowires : MOSFETs and TunnelFETs}}, url = {{https://lup.lub.lu.se/search/files/67111151/Wernersson_ULIS_2017.pdf}}, doi = {{10.1109/ULIS.2017.7962611}}, year = {{2017}}, }