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Properties of III-V nanowires : MOSFETs and TunnelFETs

Wernersson, Lars Erik LU (2017) 2017 Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 In Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings p.99-100
Abstract

This paper describes the properties and performance status of vertical III-V nanowire transistors. The development of key process modules has advanced the vertical fabrication technology and competitive device performance is reported for InAs MOSFETs and TunnelFETs. Besides the benefits in electrostatic control and the ease in integration on Si substrates, the vertical transistors offers a path towards 3D device integration as demonstrated by the stacked track-and-hold circuit where a capacitor is integrated on top of the vertical transistor for area reduction.

Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
III-V MOSFETs, III-V nanowires, InAs, InAs//GaSb, TFETs
in
Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings
issue
INSPEC Accession Number: 16998248
pages
2 pages
publisher
Institute of Electrical and Electronics Engineers Inc.
conference name
2017 Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017
external identifiers
  • scopus:85026749104
ISSN
2472-9132
ISBN
9781509053131
DOI
10.1109/ULIS.2017.7962611
language
English
LU publication?
yes
id
22571e13-3272-4922-9de4-1d0e592ab84f
date added to LUP
2017-08-31 15:57:54
date last changed
2018-01-07 12:16:57
@inproceedings{22571e13-3272-4922-9de4-1d0e592ab84f,
  abstract     = {<p>This paper describes the properties and performance status of vertical III-V nanowire transistors. The development of key process modules has advanced the vertical fabrication technology and competitive device performance is reported for InAs MOSFETs and TunnelFETs. Besides the benefits in electrostatic control and the ease in integration on Si substrates, the vertical transistors offers a path towards 3D device integration as demonstrated by the stacked track-and-hold circuit where a capacitor is integrated on top of the vertical transistor for area reduction.</p>},
  author       = {Wernersson, Lars Erik},
  booktitle    = {Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings},
  isbn         = {9781509053131},
  issn         = {2472-9132},
  keyword      = {III-V MOSFETs,III-V nanowires,InAs,InAs//GaSb,TFETs},
  language     = {eng},
  month        = {06},
  number       = {INSPEC Accession Number: 16998248 },
  pages        = {99--100},
  publisher    = {Institute of Electrical and Electronics Engineers Inc.},
  title        = {Properties of III-V nanowires : MOSFETs and TunnelFETs},
  url          = {http://dx.doi.org/10.1109/ULIS.2017.7962611},
  year         = {2017},
}