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Multiple Constraints Driven System-on-Chip Test Time Optimization

Larsson, Erik LU ; Pouget, Julien and Peng, Zebo (2005) In Journal of Electronic Testing 21(6). p.599-611
Abstract
The cost oftesting SOCs (systems-on-chip) is highly related to the testapplication time. The problem is that the test application timeincreases as the technology makes it possible to design highlycomplex chips. These complex chips include a high number of faultsites, which need a high test data volume for testing, and the hightest data volume leads to long test application times. For modularcore-based SOCs where each module has its distinct tests,concurrent application of the tests can reduce the test applicationtime dramatically, as compared to sequential application. However,when concurrent testing is used, resource conflicts and constraintsmust be considered. In this paper, we propose a test schedulingtechnique with the objective to... (More)
The cost oftesting SOCs (systems-on-chip) is highly related to the testapplication time. The problem is that the test application timeincreases as the technology makes it possible to design highlycomplex chips. These complex chips include a high number of faultsites, which need a high test data volume for testing, and the hightest data volume leads to long test application times. For modularcore-based SOCs where each module has its distinct tests,concurrent application of the tests can reduce the test applicationtime dramatically, as compared to sequential application. However,when concurrent testing is used, resource conflicts and constraintsmust be considered. In this paper, we propose a test schedulingtechnique with the objective to minimize the test application timewhile considering multiple conflicts. The conflicts we areconsidering are due to cross-core testing (testing ofinterconnections between cores), module testing with multiple testsets, hierarchical conflicts in SOCs where cores are embedded incores, the sharing of the TAM (test access mechanism), test powerlimitations, and precedence conflicts where the order in whichtests are applied is important. These conflicts must be consideredin order to design a test schedule that can be used in practice. Inparticular, the limitation on the test power consumption isimportant to consider since exceeding the system's power limitmight damage the system. We have implemented a technique tointegrate the wrapper design algorithm with the test schedulingalgorithm, while taking into account all the above constraints.Extensive experiments on the ITC'02 benchmarks show that eventhough we consider a high number of constraints, our techniqueproduces results that are in the range of results produced betechniques where the constraints are not taken intoaccount. (Less)
Please use this url to cite or link to this publication:
author
publishing date
type
Contribution to journal
publication status
published
subject
keywords
testing, system-on-chip, test access mechanism, TAM, test optimization
in
Journal of Electronic Testing
volume
21
issue
6
pages
599 - 611
publisher
Springer
external identifiers
  • scopus:27844496593
ISSN
0923-8174
DOI
10.1007/s10836-005-2911-4
language
English
LU publication?
no
id
d3dc1ed9-3823-4a79-b7de-49a4d61be30d (old id 2341058)
date added to LUP
2012-02-10 13:37:57
date last changed
2017-01-01 07:38:51
@article{d3dc1ed9-3823-4a79-b7de-49a4d61be30d,
  abstract     = {The cost oftesting SOCs (systems-on-chip) is highly related to the testapplication time. The problem is that the test application timeincreases as the technology makes it possible to design highlycomplex chips. These complex chips include a high number of faultsites, which need a high test data volume for testing, and the hightest data volume leads to long test application times. For modularcore-based SOCs where each module has its distinct tests,concurrent application of the tests can reduce the test applicationtime dramatically, as compared to sequential application. However,when concurrent testing is used, resource conflicts and constraintsmust be considered. In this paper, we propose a test schedulingtechnique with the objective to minimize the test application timewhile considering multiple conflicts. The conflicts we areconsidering are due to cross-core testing (testing ofinterconnections between cores), module testing with multiple testsets, hierarchical conflicts in SOCs where cores are embedded incores, the sharing of the TAM (test access mechanism), test powerlimitations, and precedence conflicts where the order in whichtests are applied is important. These conflicts must be consideredin order to design a test schedule that can be used in practice. Inparticular, the limitation on the test power consumption isimportant to consider since exceeding the system's power limitmight damage the system. We have implemented a technique tointegrate the wrapper design algorithm with the test schedulingalgorithm, while taking into account all the above constraints.Extensive experiments on the ITC'02 benchmarks show that eventhough we consider a high number of constraints, our techniqueproduces results that are in the range of results produced betechniques where the constraints are not taken intoaccount.},
  author       = {Larsson, Erik and Pouget, Julien and Peng, Zebo},
  issn         = {0923-8174},
  keyword      = {testing,system-on-chip,test access mechanism,TAM,test optimization},
  language     = {eng},
  number       = {6},
  pages        = {599--611},
  publisher    = {Springer},
  series       = {Journal of Electronic Testing},
  title        = {Multiple Constraints Driven System-on-Chip Test Time Optimization},
  url          = {http://dx.doi.org/10.1007/s10836-005-2911-4},
  volume       = {21},
  year         = {2005},
}