Advanced

Integrated Test Scheduling, Test Parallelization and TAM Design

Larsson, Erik LU ; Arvidsson, Klas; Fujiwara, Hideo and Peng, Zebo (2002) IEEE Asian Test Symposium ATS02 In [Host publication title missing] p.397-404
Abstract
We propose a technique integrating test scheduling, scan chain partitioning and test access mechanism (TAM) design minimizing the test time and the TAM routing cost while considering test conflicts and power constraints. Main features of our technique are (1) the flexibility in modelling the systems test behaviour and (2) the support for interconnection test of unwrapped cores and user-defined logic. Experiments using our implementation on several benchmarks and industrial designs demonstrate that it produces high quality solution at low computational cost.
Please use this url to cite or link to this publication:
author
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
test access mechanism, TAM, TAM routing, test scheduling, scan chain partitioning, test conflicts, power constraints
in
[Host publication title missing]
pages
397 - 404
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
IEEE Asian Test Symposium ATS02
external identifiers
  • scopus:0142237005
ISSN
1081-7735
ISBN
0-7695-1825-7
DOI
10.1109/ATS.2002.1181744
language
English
LU publication?
no
id
05e1d002-6d26-4dfa-8370-4239620daa20 (old id 2341114)
date added to LUP
2012-02-10 13:32:15
date last changed
2017-01-01 06:40:04
@inproceedings{05e1d002-6d26-4dfa-8370-4239620daa20,
  abstract     = {We propose a technique integrating test scheduling, scan chain partitioning and test access mechanism (TAM) design minimizing the test time and the TAM routing cost while considering test conflicts and power constraints. Main features of our technique are (1) the flexibility in modelling the systems test behaviour and (2) the support for interconnection test of unwrapped cores and user-defined logic. Experiments using our implementation on several benchmarks and industrial designs demonstrate that it produces high quality solution at low computational cost.},
  author       = {Larsson, Erik and Arvidsson, Klas and Fujiwara, Hideo and Peng, Zebo},
  booktitle    = {[Host publication title missing]},
  isbn         = {0-7695-1825-7},
  issn         = {1081-7735},
  keyword      = {test access mechanism,TAM,TAM routing,test scheduling,scan chain partitioning,test conflicts,power constraints},
  language     = {eng},
  pages        = {397--404},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  title        = {Integrated Test Scheduling, Test Parallelization and TAM Design},
  url          = {http://dx.doi.org/10.1109/ATS.2002.1181744},
  year         = {2002},
}