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Optimal System-on-Chip Test Scheduling

Larsson, Erik LU and Fujiwara, Hideo (2003) 12th IEEE Asian Test Symposium ATS03 In [Host publication title missing] p.306-311
Abstract
In this paper, we show that the scheduling of tests on the test access mechanism (TAM) is equivalent to independent job scheduling on identical machines and we make use of an existing preemptive scheduling algorithm to produce an optimal solution in linear time. We extend the algorithm to handle (1) test conflicts due to interconnection tests and (2) cases when a test limits an optimal usage of the TAM by using reconfigurable core test wrappers. Our extensions preserve the production of an optimal solution in respect to test time and minimizes the number of wrapper configurations as well as the TAM usage at each core, which implicitly minimizes the TAM routing. Experiments with our implementation shows its efficiency in comparison with... (More)
In this paper, we show that the scheduling of tests on the test access mechanism (TAM) is equivalent to independent job scheduling on identical machines and we make use of an existing preemptive scheduling algorithm to produce an optimal solution in linear time. We extend the algorithm to handle (1) test conflicts due to interconnection tests and (2) cases when a test limits an optimal usage of the TAM by using reconfigurable core test wrappers. Our extensions preserve the production of an optimal solution in respect to test time and minimizes the number of wrapper configurations as well as the TAM usage at each core, which implicitly minimizes the TAM routing. Experiments with our implementation shows its efficiency in comparison with previous approaches. (Less)
Please use this url to cite or link to this publication:
author
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
test scheduling, test access mechanisms, TAM, test conflicts, test wrappers, TAM routing
in
[Host publication title missing]
pages
306 - 311
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
12th IEEE Asian Test Symposium ATS03
external identifiers
  • scopus:34648833691
ISSN
1081-7735
ISBN
0-7695-1951-2
DOI
10.1109/ATS.2003.1250828
language
English
LU publication?
no
id
8a67b755-a480-4317-a4a4-cd6606ca4849 (old id 2341143)
date added to LUP
2012-02-10 13:29:20
date last changed
2017-06-11 04:37:14
@inproceedings{8a67b755-a480-4317-a4a4-cd6606ca4849,
  abstract     = {In this paper, we show that the scheduling of tests on the test access mechanism (TAM) is equivalent to independent job scheduling on identical machines and we make use of an existing preemptive scheduling algorithm to produce an optimal solution in linear time. We extend the algorithm to handle (1) test conflicts due to interconnection tests and (2) cases when a test limits an optimal usage of the TAM by using reconfigurable core test wrappers. Our extensions preserve the production of an optimal solution in respect to test time and minimizes the number of wrapper configurations as well as the TAM usage at each core, which implicitly minimizes the TAM routing. Experiments with our implementation shows its efficiency in comparison with previous approaches.},
  author       = {Larsson, Erik and Fujiwara, Hideo},
  booktitle    = {[Host publication title missing]},
  isbn         = {0-7695-1951-2},
  issn         = {1081-7735},
  keyword      = {test scheduling,test access mechanisms,TAM,test conflicts,test wrappers,TAM routing},
  language     = {eng},
  pages        = {306--311},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  title        = {Optimal System-on-Chip Test Scheduling},
  url          = {http://dx.doi.org/10.1109/ATS.2003.1250828},
  year         = {2003},
}