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Defect-Aware SOC Test Scheduling

Larsson, Erik LU ; Pouget, Julien and Peng, Zebo (2004) 2004 IEEE VLSI Test Symposium VTS04 In VLSI Test Symposium, 2004. Proceedings. 22nd IEEE p.359-364
Abstract
In this paper we address the test scheduling problem for system-on-chip designs. Different from previous approaches where it is assumed that all tests will be performed until completion, we consider the cases where the test process will be terminated as soon as a defect is detected. This is common practice in production test of chips. The proposed technique takes into account the probability of defect-detection by a test in order to schedule the tests so that the expected total test time will be minimized. We investigate different test bus structures, test scheduling strategies (sequential scheduling vs. Concurrent scheduling), and test set assumptions (fixed test time vs. Flexible test time). We have also made experiments to illustrate... (More)
In this paper we address the test scheduling problem for system-on-chip designs. Different from previous approaches where it is assumed that all tests will be performed until completion, we consider the cases where the test process will be terminated as soon as a defect is detected. This is common practice in production test of chips. The proposed technique takes into account the probability of defect-detection by a test in order to schedule the tests so that the expected total test time will be minimized. We investigate different test bus structures, test scheduling strategies (sequential scheduling vs. Concurrent scheduling), and test set assumptions (fixed test time vs. Flexible test time). We have also made experiments to illustrate the efficiency of taking defect probability into account during test scheduling. (Less)
Please use this url to cite or link to this publication:
author
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
system-on-chip, defect-detection, test scheduling, sequential scheduling, concurrent scheduling, defect probabilities
in
VLSI Test Symposium, 2004. Proceedings. 22nd IEEE
pages
359 - 364
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
2004 IEEE VLSI Test Symposium VTS04
external identifiers
  • scopus:3142752834
ISSN
1093-0167
ISBN
0-7695-2134-7
DOI
10.1109/VTEST.2004.1299265
language
English
LU publication?
no
id
879cfa2b-0ada-4dcd-a3a6-b5e2e8717b04 (old id 2341150)
date added to LUP
2012-02-10 13:26:57
date last changed
2017-09-10 04:24:13
@inproceedings{879cfa2b-0ada-4dcd-a3a6-b5e2e8717b04,
  abstract     = {In this paper we address the test scheduling problem for system-on-chip designs. Different from previous approaches where it is assumed that all tests will be performed until completion, we consider the cases where the test process will be terminated as soon as a defect is detected. This is common practice in production test of chips. The proposed technique takes into account the probability of defect-detection by a test in order to schedule the tests so that the expected total test time will be minimized. We investigate different test bus structures, test scheduling strategies (sequential scheduling vs. Concurrent scheduling), and test set assumptions (fixed test time vs. Flexible test time). We have also made experiments to illustrate the efficiency of taking defect probability into account during test scheduling.},
  author       = {Larsson, Erik and Pouget, Julien and Peng, Zebo},
  booktitle    = {VLSI Test Symposium, 2004. Proceedings. 22nd IEEE},
  isbn         = {0-7695-2134-7},
  issn         = {1093-0167},
  keyword      = {system-on-chip,defect-detection,test scheduling,sequential scheduling,concurrent scheduling,defect probabilities},
  language     = {eng},
  pages        = {359--364},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  title        = {Defect-Aware SOC Test Scheduling},
  url          = {http://dx.doi.org/10.1109/VTEST.2004.1299265},
  year         = {2004},
}