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A single-stage direct interpolation multiphase clock generator with phase error averaging

Lixin, Yang LU and Yuan, Jiren LU (2004) In Analog Integrated Circuits and Signal Processing 38(1). p.17-26
Abstract
Multiphase clock generators are conventionally implemented with a feedback loop. This paper presents a non-feedback approach to generate multiphase clocks. A simple architecture of direct phase interpolation is proposed, in which the edges of two phase-adjacent signals are used to control the discharge (or charge) of two capacitors respectively, producing time-overlapped slopes. A resistor chain connected to the two capacitors is used to interpolate a number of new slopes in between. The generated phase resolution depends on the number and ratios of resistors thus is not limited by an inverter delay. Based on this architecture, a multiphase clock generator is developed. In addition, a phase error averaging circuit is used to correct... (More)
Multiphase clock generators are conventionally implemented with a feedback loop. This paper presents a non-feedback approach to generate multiphase clocks. A simple architecture of direct phase interpolation is proposed, in which the edges of two phase-adjacent signals are used to control the discharge (or charge) of two capacitors respectively, producing time-overlapped slopes. A resistor chain connected to the two capacitors is used to interpolate a number of new slopes in between. The generated phase resolution depends on the number and ratios of resistors thus is not limited by an inverter delay. Based on this architecture, a multiphase clock generator is developed. In addition, a phase error averaging circuit is used to correct interphase errors. The multiphase clock generator has been fabricated in a 0.35 mum, 3.3 V CMOS process. The measured performance shows it can produce 8 evenly spaced clock signals in one input clock period and work in an input clock range from 300 MHz to 600 MHz. The measured maximum jitter performance is rms 6.8 ps and peak-to-peak 47 ps, respectively. (Less)
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author
organization
publishing date
type
Contribution to journal
publication status
published
subject
keywords
multiphase, non-feedback, clock generator, phase interpolation
in
Analog Integrated Circuits and Signal Processing
volume
38
issue
1
pages
17 - 26
publisher
Springer
external identifiers
  • wos:000185570600003
  • scopus:0347762706
ISSN
0925-1030
DOI
10.1023/A:1025842120155
language
English
LU publication?
yes
id
19c94ac1-b2dc-414a-917b-ca95984bb4bc (old id 299934)
date added to LUP
2007-11-07 08:10:20
date last changed
2017-01-01 07:19:42
@article{19c94ac1-b2dc-414a-917b-ca95984bb4bc,
  abstract     = {Multiphase clock generators are conventionally implemented with a feedback loop. This paper presents a non-feedback approach to generate multiphase clocks. A simple architecture of direct phase interpolation is proposed, in which the edges of two phase-adjacent signals are used to control the discharge (or charge) of two capacitors respectively, producing time-overlapped slopes. A resistor chain connected to the two capacitors is used to interpolate a number of new slopes in between. The generated phase resolution depends on the number and ratios of resistors thus is not limited by an inverter delay. Based on this architecture, a multiphase clock generator is developed. In addition, a phase error averaging circuit is used to correct interphase errors. The multiphase clock generator has been fabricated in a 0.35 mum, 3.3 V CMOS process. The measured performance shows it can produce 8 evenly spaced clock signals in one input clock period and work in an input clock range from 300 MHz to 600 MHz. The measured maximum jitter performance is rms 6.8 ps and peak-to-peak 47 ps, respectively.},
  author       = {Lixin, Yang and Yuan, Jiren},
  issn         = {0925-1030},
  keyword      = {multiphase,non-feedback,clock generator,phase interpolation},
  language     = {eng},
  number       = {1},
  pages        = {17--26},
  publisher    = {Springer},
  series       = {Analog Integrated Circuits and Signal Processing},
  title        = {A single-stage direct interpolation multiphase clock generator with phase error averaging},
  url          = {http://dx.doi.org/10.1023/A:1025842120155},
  volume       = {38},
  year         = {2004},
}