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Three-Dimensional Integration of InAs Nanowires by Template-Assisted Selective Epitaxy on Tungsten

Svensson, Johannes LU ; Olausson, Patrik LU ; Menon, Heera LU ; Lehmann, Sebastian LU ; Lind, Erik LU and Borg, Mattias LU orcid (2023) In Nano Letters 23(11). p.4756-4761
Abstract

3D integration of III-V semiconductors with Si CMOS is highly attractive since it allows combining new functions such as photonic and analog devices with digital signal processing circuitry. Thus far, most 3D integration approaches have used epitaxial growth on Si, layer transfer by wafer bonding, or die-to-die packaging. Here we present low-temperature integration of InAs on W using Si3N4 template assisted selective area metal-organic vapor-phase epitaxy (MOVPE). Despite growth nucleation on polycrystalline W, we can obtain a high yield of single-crystalline InAs nanowires, as observed by transmission electron microscopy (TEM) and electron backscatter diffraction (EBSD). The nanowires exhibit a mobility of 690 cm2/(V s), a... (More)

3D integration of III-V semiconductors with Si CMOS is highly attractive since it allows combining new functions such as photonic and analog devices with digital signal processing circuitry. Thus far, most 3D integration approaches have used epitaxial growth on Si, layer transfer by wafer bonding, or die-to-die packaging. Here we present low-temperature integration of InAs on W using Si3N4 template assisted selective area metal-organic vapor-phase epitaxy (MOVPE). Despite growth nucleation on polycrystalline W, we can obtain a high yield of single-crystalline InAs nanowires, as observed by transmission electron microscopy (TEM) and electron backscatter diffraction (EBSD). The nanowires exhibit a mobility of 690 cm2/(V s), a low-resistive, Ohmic electrical contact to the W film, and a resistivity which increases with diameter attributed to increased grain boundary scattering. These results demonstrate the feasibility for single-crystalline III-V back-end-of-line integration with a low thermal budget compatible with Si CMOS.

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author
; ; ; ; and
organization
publishing date
type
Contribution to journal
publication status
published
subject
keywords
III-V semiconductors, InAs, metal-organic vapor-phase epitaxy, nanowires, selective area epitaxy, Si CMOS integration
in
Nano Letters
volume
23
issue
11
pages
6 pages
publisher
The American Chemical Society (ACS)
external identifiers
  • pmid:37227403
  • scopus:85162800046
ISSN
1530-6984
DOI
10.1021/acs.nanolett.2c04908
project
III-V Devices for Emerging Electronic Applications
Integration of III-V semiconductor on Si by Rapid Melt Growth
language
English
LU publication?
yes
additional info
Funding Information: This research was supported by NanoLund, the Crafoord foundation (Grant no. 20210658), and the Swedish Research Council (VR) (Grant 2016-00891). The authors also acknowledge the kind assistance with TEM imaging and analysis from Crispin Hetherington and Daniel Madsen, both at the Centre for Analysis and Synthesis at Lund University. Publisher Copyright: © 2023 American Chemical Society.
id
2f2e61e4-0691-4ad8-8d03-8692bd35be05
date added to LUP
2023-07-21 10:18:32
date last changed
2024-04-19 23:52:44
@article{2f2e61e4-0691-4ad8-8d03-8692bd35be05,
  abstract     = {{<p>3D integration of III-V semiconductors with Si CMOS is highly attractive since it allows combining new functions such as photonic and analog devices with digital signal processing circuitry. Thus far, most 3D integration approaches have used epitaxial growth on Si, layer transfer by wafer bonding, or die-to-die packaging. Here we present low-temperature integration of InAs on W using Si3N4 template assisted selective area metal-organic vapor-phase epitaxy (MOVPE). Despite growth nucleation on polycrystalline W, we can obtain a high yield of single-crystalline InAs nanowires, as observed by transmission electron microscopy (TEM) and electron backscatter diffraction (EBSD). The nanowires exhibit a mobility of 690 cm2/(V s), a low-resistive, Ohmic electrical contact to the W film, and a resistivity which increases with diameter attributed to increased grain boundary scattering. These results demonstrate the feasibility for single-crystalline III-V back-end-of-line integration with a low thermal budget compatible with Si CMOS.</p>}},
  author       = {{Svensson, Johannes and Olausson, Patrik and Menon, Heera and Lehmann, Sebastian and Lind, Erik and Borg, Mattias}},
  issn         = {{1530-6984}},
  keywords     = {{III-V semiconductors; InAs; metal-organic vapor-phase epitaxy; nanowires; selective area epitaxy; Si CMOS integration}},
  language     = {{eng}},
  month        = {{06}},
  number       = {{11}},
  pages        = {{4756--4761}},
  publisher    = {{The American Chemical Society (ACS)}},
  series       = {{Nano Letters}},
  title        = {{Three-Dimensional Integration of InAs Nanowires by Template-Assisted Selective Epitaxy on Tungsten}},
  url          = {{http://dx.doi.org/10.1021/acs.nanolett.2c04908}},
  doi          = {{10.1021/acs.nanolett.2c04908}},
  volume       = {{23}},
  year         = {{2023}},
}