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Performance Evaluation of III–V Nanowire Transistors

Jansson, Kristofer LU ; Lind, Erik LU and Wernersson, Lars-Erik LU (2012) In IEEE Transactions on Electron Devices 59(9). p.2375-2382
Abstract
III–V nanowire (NW) transistors are an emerging technology with the prospect of high performance and low power dissipation. Performance evaluations of these devices, however, have focused mostly on the intrinsic properties of the NW, excluding any parasitic elements. In this paper, a III–V NW transistor architecture is investigated, based on a NW array with a realistic footprint. Based on scaling rules for the structural parameters, 3-D representations of the transistor are generated, and the parasitic capacitances are calculated. A complete optimization of the structure is performed based on the RF performance metrics fT and fmax, employing intrinsic transistor data combined with calculated parasitic capacitances and resistances. The... (More)
III–V nanowire (NW) transistors are an emerging technology with the prospect of high performance and low power dissipation. Performance evaluations of these devices, however, have focused mostly on the intrinsic properties of the NW, excluding any parasitic elements. In this paper, a III–V NW transistor architecture is investigated, based on a NW array with a realistic footprint. Based on scaling rules for the structural parameters, 3-D representations of the transistor are generated, and the parasitic capacitances are calculated. A complete optimization of the structure is performed based on the RF performance metrics fT and fmax, employing intrinsic transistor data combined with calculated parasitic capacitances and resistances. The result is a roadmap of optimized transistor structures for a set of technology nodes, with gate lengths down to the 10-nm-length scale. For each technology node, the performance is predicted, promising operation in the terahertz regime. The resulting roadmap has implications as a reference both for benchmarking and for device fabrication. (Less)
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author
organization
publishing date
type
Contribution to journal
publication status
published
subject
keywords
Capacitance, Electrodes, Logic gates, Nanowires, Performance evaluation, Transistors, Field-effect transistor (FET), InAs, modeling, nanowires (NWs), roadmap
in
IEEE Transactions on Electron Devices
volume
59
issue
9
pages
2375 - 2382
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • wos:000307905200016
  • scopus:84865521712
ISSN
0018-9383
DOI
10.1109/TED.2012.2204757
project
EIT_WWW Wireless with Wires
language
English
LU publication?
yes
id
c4d727f6-51e9-479f-a8fc-cdf00b33faaf (old id 3173050)
date added to LUP
2012-11-19 14:42:55
date last changed
2017-08-27 04:58:19
@article{c4d727f6-51e9-479f-a8fc-cdf00b33faaf,
  abstract     = {III–V nanowire (NW) transistors are an emerging technology with the prospect of high performance and low power dissipation. Performance evaluations of these devices, however, have focused mostly on the intrinsic properties of the NW, excluding any parasitic elements. In this paper, a III–V NW transistor architecture is investigated, based on a NW array with a realistic footprint. Based on scaling rules for the structural parameters, 3-D representations of the transistor are generated, and the parasitic capacitances are calculated. A complete optimization of the structure is performed based on the RF performance metrics fT and fmax, employing intrinsic transistor data combined with calculated parasitic capacitances and resistances. The result is a roadmap of optimized transistor structures for a set of technology nodes, with gate lengths down to the 10-nm-length scale. For each technology node, the performance is predicted, promising operation in the terahertz regime. The resulting roadmap has implications as a reference both for benchmarking and for device fabrication.},
  author       = {Jansson, Kristofer and Lind, Erik and Wernersson, Lars-Erik},
  issn         = {0018-9383},
  keyword      = {Capacitance,Electrodes,Logic gates,Nanowires,Performance evaluation,Transistors,Field-effect transistor (FET),InAs,modeling,nanowires (NWs),roadmap},
  language     = {eng},
  number       = {9},
  pages        = {2375--2382},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  series       = {IEEE Transactions on Electron Devices},
  title        = {Performance Evaluation of III–V Nanowire Transistors},
  url          = {http://dx.doi.org/10.1109/TED.2012.2204757},
  volume       = {59},
  year         = {2012},
}