Supply-Voltage Down Conversion for Digital CMOS Designs
(2014) IEEE 21th International Conference on Electronics, Circuits and Systems, 2014- Abstract
- This paper presents a methodology to reduce the power consumption, by using multiple supply voltage levels. The voltage levels are scaled down from a single supply voltage, by the use of a diode-connected device. Only one single device is used per conversion, which gives a small area overhead. No inductors and no off-chip components are used. The methodology is tested on different constellations of inverters and on anti-aliasing filters. A power reduction down to 47% in the filters with reduced supply voltage and down to 72% in the complete filter is shown.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/4882564
- author
- Nilsson, Peter LU ; Azher Ali, Mohammed ; Ethiraj, Manivannan and Sherazi, Syed Muhammad Yasser LU
- organization
- publishing date
- 2014
- type
- Contribution to conference
- publication status
- published
- subject
- keywords
- Application specific integrated circuits, digital circuits, CMOS integrated circuits, digital filters, low-pass filters, low-power electronics, and DC-DC converters.
- pages
- 4 pages
- conference name
- IEEE 21th International Conference on Electronics, Circuits and Systems, 2014
- conference location
- Marseille, France
- conference dates
- 2014-12-07 - 2014-12-10
- language
- English
- LU publication?
- yes
- id
- 9f4515da-1528-4a2a-bc7f-f922d000ca88 (old id 4882564)
- date added to LUP
- 2016-04-04 14:28:16
- date last changed
- 2018-11-21 21:20:30
@misc{9f4515da-1528-4a2a-bc7f-f922d000ca88, abstract = {{This paper presents a methodology to reduce the power consumption, by using multiple supply voltage levels. The voltage levels are scaled down from a single supply voltage, by the use of a diode-connected device. Only one single device is used per conversion, which gives a small area overhead. No inductors and no off-chip components are used. The methodology is tested on different constellations of inverters and on anti-aliasing filters. A power reduction down to 47% in the filters with reduced supply voltage and down to 72% in the complete filter is shown.}}, author = {{Nilsson, Peter and Azher Ali, Mohammed and Ethiraj, Manivannan and Sherazi, Syed Muhammad Yasser}}, keywords = {{Application specific integrated circuits; digital circuits; CMOS integrated circuits; digital filters; low-pass filters; low-power electronics; and DC-DC converters.}}, language = {{eng}}, title = {{Supply-Voltage Down Conversion for Digital CMOS Designs}}, year = {{2014}}, }