Capacitance Scaling in In0.71Ga0.29As/InP MOSFETs with Self-Aligned a:Si Spacers
(2021) In IEEE Transactions on Electron Devices 68(8). p.3762-3767- Abstract
In0.71Ga0.29As/InP (12/2 nm) quantum well MOSFETs using sacrificial amorphous silicon (a:Si) spacers to achieve low parasitic capacitance are fabricated. Radio frequency characterization of 73 devices is used to study the intrinsic and extrinsic capacitances. The total gate intrinsic parasitic capacitance of 0.55 fF/μm is achieved with an intrinsic gate capacitance of 0.39 μF/cm2. The various parasitic capacitances are modeled using finite element electrostatic simulations, and semi-analytical expressions are provided. A device with a gate length Lg=80 nm has SS min=168 mV/dec, dc transconductance gm,e =1.0 mS μ m at VDS=0.5 V, and exhibits a peak cutoff frequency it fT of 243 GHz, and a maximum oscillation frequency it fmax of 147 GHz... (More)
In0.71Ga0.29As/InP (12/2 nm) quantum well MOSFETs using sacrificial amorphous silicon (a:Si) spacers to achieve low parasitic capacitance are fabricated. Radio frequency characterization of 73 devices is used to study the intrinsic and extrinsic capacitances. The total gate intrinsic parasitic capacitance of 0.55 fF/μm is achieved with an intrinsic gate capacitance of 0.39 μF/cm2. The various parasitic capacitances are modeled using finite element electrostatic simulations, and semi-analytical expressions are provided. A device with a gate length Lg=80 nm has SS min=168 mV/dec, dc transconductance gm,e =1.0 mS μ m at VDS=0.5 V, and exhibits a peak cutoff frequency it fT of 243 GHz, and a maximum oscillation frequency it fmax of 147 GHz at VGS=0.25 V, VDS= 1 V.
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- author
- Garigapati, Navya S. LU ; Lindelow, Fredrik LU ; Sodergren, Lasse LU and Lind, Erik LU
- organization
- publishing date
- 2021
- type
- Contribution to journal
- publication status
- published
- subject
- keywords
- amorphous silicon (a:Si), capacitance, hydrogen silsesquioxane (HSQ), III-V compound semiconductor, MOSFET
- in
- IEEE Transactions on Electron Devices
- volume
- 68
- issue
- 8
- article number
- 9477554
- pages
- 6 pages
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- external identifiers
-
- scopus:85111618416
- ISSN
- 0018-9383
- DOI
- 10.1109/TED.2021.3092299
- language
- English
- LU publication?
- yes
- id
- 57e70a89-7d9f-4712-aae1-147290c2126c
- date added to LUP
- 2021-08-27 10:13:29
- date last changed
- 2023-10-10 23:46:08
@article{57e70a89-7d9f-4712-aae1-147290c2126c,
abstract = {{<p>In0.71Ga0.29As/InP (12/2 nm) quantum well MOSFETs using sacrificial amorphous silicon (a:Si) spacers to achieve low parasitic capacitance are fabricated. Radio frequency characterization of 73 devices is used to study the intrinsic and extrinsic capacitances. The total gate intrinsic parasitic capacitance of 0.55 fF/μm is achieved with an intrinsic gate capacitance of 0.39 μF/cm2. The various parasitic capacitances are modeled using finite element electrostatic simulations, and semi-analytical expressions are provided. A device with a gate length Lg=80 nm has SS min=168 mV/dec, dc transconductance gm,e =1.0 mS μ m at VDS=0.5 V, and exhibits a peak cutoff frequency it fT of 243 GHz, and a maximum oscillation frequency it fmax of 147 GHz at VGS=0.25 V, VDS= 1 V. </p>}},
author = {{Garigapati, Navya S. and Lindelow, Fredrik and Sodergren, Lasse and Lind, Erik}},
issn = {{0018-9383}},
keywords = {{amorphous silicon (a:Si); capacitance; hydrogen silsesquioxane (HSQ); III-V compound semiconductor; MOSFET}},
language = {{eng}},
number = {{8}},
pages = {{3762--3767}},
publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
series = {{IEEE Transactions on Electron Devices}},
title = {{Capacitance Scaling in In<sub>0.71</sub>Ga<sub>0.29</sub>As/InP MOSFETs with Self-Aligned a:Si Spacers}},
url = {{http://dx.doi.org/10.1109/TED.2021.3092299}},
doi = {{10.1109/TED.2021.3092299}},
volume = {{68}},
year = {{2021}},
}