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A differential difference comparator for multi-step A/D converters

Xu, Gang LU and Yuan, Jiren LU (2003) Proceedings of the 2003 IEEE International Symposium on Circuits and Systems 1. p.257-260
Abstract
The proposed Differential Difference Comparator (DDC) provides easy linear voltage summing/subtraction and comparison functions via current operation. The speed of this unconventional comparator drastically improved since there is no feedback loop and coupling capacitors needed to maintain the linearity. The linear input range is also enlarged by the common mode compression. The principle, design considerations and simulation results are presented based on a comparator used in an 8 bit 2-step A/D converter over 100 MS/s.
Please use this url to cite or link to this publication:
author
and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
Differential difference comparators (DDC)
host publication
Proceedings - IEEE International Symposium on Circuits and Systems
volume
1
pages
257 - 260
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
conference name
Proceedings of the 2003 IEEE International Symposium on Circuits and Systems
conference location
Bangkok, Thailand
conference dates
2003-05-25 - 2003-05-28
external identifiers
  • wos:000184716700065
  • scopus:0037482970
ISSN
2158-1525
0271-4310
language
English
LU publication?
yes
id
c834bc19-4b54-4660-9d63-a7d7f4459d3d (old id 612226)
date added to LUP
2016-04-01 12:33:31
date last changed
2024-01-09 00:45:40
@inproceedings{c834bc19-4b54-4660-9d63-a7d7f4459d3d,
  abstract     = {{The proposed Differential Difference Comparator (DDC) provides easy linear voltage summing/subtraction and comparison functions via current operation. The speed of this unconventional comparator drastically improved since there is no feedback loop and coupling capacitors needed to maintain the linearity. The linear input range is also enlarged by the common mode compression. The principle, design considerations and simulation results are presented based on a comparator used in an 8 bit 2-step A/D converter over 100 MS/s.}},
  author       = {{Xu, Gang and Yuan, Jiren}},
  booktitle    = {{Proceedings - IEEE International Symposium on Circuits and Systems}},
  issn         = {{2158-1525}},
  keywords     = {{Differential difference comparators (DDC)}},
  language     = {{eng}},
  pages        = {{257--260}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  title        = {{A differential difference comparator for multi-step A/D converters}},
  volume       = {{1}},
  year         = {{2003}},
}