An arbitrarily skewable multiphase clock generator combining direct interpolation with phase error average
(2003) Proceedings of the 2003 IEEE International Symposium on Circuits and Systems 1. p.645-648- Abstract
- A multiphase clock generator based on direct phase interpolation is presented. No feedback loop is required. A simple phase interpolation architecture is proposed, in which the two phase-adjacent signals are interpolated by using a series of resistors via inverters' discharging or charging slopes to generate multiphase outputs in a single stage. A phase error averaging circuit is used to correct interphase errors. The multiphase clock generator has been fabricated in a standard 0.35 μm, 3.3 V CMOS process. The measured performance shows it can operate at the input clock frequencies from 300 MHz to 600 MHz and has the rms jitter of 6 ps at 500 MHz.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/613136
- author
- Lixin, Yang LU and Yuan, Jiren LU
- organization
- publishing date
- 2003
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- keywords
- Multiphase clock generators
- host publication
- Proceedings - IEEE International Symposium on Circuits and Systems
- volume
- 1
- pages
- 645 - 648
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- Proceedings of the 2003 IEEE International Symposium on Circuits and Systems
- conference location
- Bangkok, Thailand
- conference dates
- 2003-05-25 - 2003-05-28
- external identifiers
-
- wos:000184716700162
- other:CODEN: PICSDI
- scopus:0037812926
- ISSN
- 2158-1525
- 0271-4310
- DOI
- 10.1109/ISCAS.2003.1205646
- language
- English
- LU publication?
- yes
- id
- 6225d4d6-c60e-42f1-a9f6-3fc68d388f67 (old id 613136)
- date added to LUP
- 2016-04-01 12:09:55
- date last changed
- 2024-01-08 10:43:31
@inproceedings{6225d4d6-c60e-42f1-a9f6-3fc68d388f67, abstract = {{A multiphase clock generator based on direct phase interpolation is presented. No feedback loop is required. A simple phase interpolation architecture is proposed, in which the two phase-adjacent signals are interpolated by using a series of resistors via inverters' discharging or charging slopes to generate multiphase outputs in a single stage. A phase error averaging circuit is used to correct interphase errors. The multiphase clock generator has been fabricated in a standard 0.35 μm, 3.3 V CMOS process. The measured performance shows it can operate at the input clock frequencies from 300 MHz to 600 MHz and has the rms jitter of 6 ps at 500 MHz.}}, author = {{Lixin, Yang and Yuan, Jiren}}, booktitle = {{Proceedings - IEEE International Symposium on Circuits and Systems}}, issn = {{2158-1525}}, keywords = {{Multiphase clock generators}}, language = {{eng}}, pages = {{645--648}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, title = {{An arbitrarily skewable multiphase clock generator combining direct interpolation with phase error average}}, url = {{http://dx.doi.org/10.1109/ISCAS.2003.1205646}}, doi = {{10.1109/ISCAS.2003.1205646}}, volume = {{1}}, year = {{2003}}, }