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An arbitrarily skewable multiphase clock generator combining direct interpolation with phase error average

Lixin, Yang LU and Yuan, Jiren LU (2003) Proceedings of the 2003 IEEE International Symposium on Circuits and Systems In Proceedings - IEEE International Symposium on Circuits and Systems 1. p.645-648
Abstract
A multiphase clock generator based on direct phase interpolation is presented. No feedback loop is required. A simple phase interpolation architecture is proposed, in which the two phase-adjacent signals are interpolated by using a series of resistors via inverters' discharging or charging slopes to generate multiphase outputs in a single stage. A phase error averaging circuit is used to correct interphase errors. The multiphase clock generator has been fabricated in a standard 0.35 μm, 3.3 V CMOS process. The measured performance shows it can operate at the input clock frequencies from 300 MHz to 600 MHz and has the rms jitter of 6 ps at 500 MHz.
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author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
Multiphase clock generators
in
Proceedings - IEEE International Symposium on Circuits and Systems
volume
1
pages
645 - 648
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
Proceedings of the 2003 IEEE International Symposium on Circuits and Systems
external identifiers
  • wos:000184716700162
  • other:CODEN: PICSDI
  • scopus:0037812926
ISSN
0271-4310
2158-1525
DOI
10.1109/ISCAS.2003.1205646
language
English
LU publication?
yes
id
6225d4d6-c60e-42f1-a9f6-3fc68d388f67 (old id 613136)
date added to LUP
2007-11-29 11:36:30
date last changed
2018-05-29 10:53:42
@inproceedings{6225d4d6-c60e-42f1-a9f6-3fc68d388f67,
  abstract     = {A multiphase clock generator based on direct phase interpolation is presented. No feedback loop is required. A simple phase interpolation architecture is proposed, in which the two phase-adjacent signals are interpolated by using a series of resistors via inverters' discharging or charging slopes to generate multiphase outputs in a single stage. A phase error averaging circuit is used to correct interphase errors. The multiphase clock generator has been fabricated in a standard 0.35 μm, 3.3 V CMOS process. The measured performance shows it can operate at the input clock frequencies from 300 MHz to 600 MHz and has the rms jitter of 6 ps at 500 MHz.},
  author       = {Lixin, Yang and Yuan, Jiren},
  booktitle    = {Proceedings - IEEE International Symposium on Circuits and Systems},
  issn         = {0271-4310},
  keyword      = {Multiphase clock generators},
  language     = {eng},
  pages        = {645--648},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  title        = {An arbitrarily skewable multiphase clock generator combining direct interpolation with phase error average},
  url          = {http://dx.doi.org/10.1109/ISCAS.2003.1205646},
  volume       = {1},
  year         = {2003},
}