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Lateral III-V Nanowire MOSFETs in Low-Noise Amplifier Stages

Andric, Stefan LU ; Lindelow, Fredrik LU ; Fhager, Lars Ohlsson LU orcid ; Lind, Erik LU orcid and Wernersson, Lars Erik LU (2022) In IEEE Transactions on Microwave Theory and Techniques 70(2). p.1284-1291
Abstract

Lateral III-V nanowire (NW) MOSFETs are a promising candidate for high-frequency electronics. However, their circuit performance is not yet assessed. Here, we integrate lateral nanowires (LNWs) in a circuit environment and characterize the transistors and amplifiers. MOSFETs are fabricated in a simple scheme with a dc transconductance of up to 1.3 mS/μm, ON-resistance down to 265 Ω · μ m, and cutoff frequencies up to 250 GHz, measured on the circuit level. The circuit model estimates 25% device parasitic capacitance increase due to back-end-of-line (BEOL) dielectric cladding. A low-noise amplifier input stage is designed with optimum network design for a noise matched input and an... (More)

Lateral III-V nanowire (NW) MOSFETs are a promising candidate for high-frequency electronics. However, their circuit performance is not yet assessed. Here, we integrate lateral nanowires (LNWs) in a circuit environment and characterize the transistors and amplifiers. MOSFETs are fabricated in a simple scheme with a dc transconductance of up to 1.3 mS/μm, ON-resistance down to 265 Ω · μ m, and cutoff frequencies up to 250 GHz, measured on the circuit level. The circuit model estimates 25% device parasitic capacitance increase due to back-end-of-line (BEOL) dielectric cladding. A low-noise amplifier input stage is designed with optimum network design for a noise matched input and an inductive peaking output. The input stage shows up to 4-dB gain and 2.5-dB noise figure (NF), at 60 GHz. Utilizing gate-length scaling in the circuit environment, the obtained normalized intrinsic gate capacitance value of 0.34-aF/nm gate length, per NW, corresponds well to the predicted theoretical value, demonstrating the circuit's ability to provide intrinsic device parameters. This is the first mm-wave validation of noise models for III-V LNW MOSFETs. The results demonstrate the potential for utilization of the technology platform for low-noise applications.

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author
; ; ; and
organization
publishing date
type
Contribution to journal
publication status
published
subject
keywords
Back-end-of-line (BEOL), capacitance modeling, Dielectrics, front-end-of-line (FEOL), III-V., InGaAs, lateral, LNA, Logic gates, MOSFET, nanowire (NW), NW circuits, Parasitic capacitance, Photomicrography, Radio frequency, Semiconductor device modeling
in
IEEE Transactions on Microwave Theory and Techniques
volume
70
issue
2
pages
1284 - 1291
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • scopus:85118989274
ISSN
0018-9480
DOI
10.1109/TMTT.2021.3124088
language
English
LU publication?
yes
additional info
Publisher Copyright: IEEE
id
61f87eb8-9ea2-4bad-a811-b80cf0ea453b
date added to LUP
2021-12-02 15:49:18
date last changed
2024-08-11 02:47:30
@article{61f87eb8-9ea2-4bad-a811-b80cf0ea453b,
  abstract     = {{<p>Lateral III-V nanowire (NW) MOSFETs are a promising candidate for high-frequency electronics. However, their circuit performance is not yet assessed. Here, we integrate lateral nanowires (LNWs) in a circuit environment and characterize the transistors and amplifiers. MOSFETs are fabricated in a simple scheme with a dc transconductance of up to 1.3 mS/&amp;#x03BC;m, ON-resistance down to 265 &amp;#x03A9; &amp;#x00B7; &amp;#x03BC; m, and cutoff frequencies up to 250 GHz, measured on the circuit level. The circuit model estimates 25&amp;#x0025; device parasitic capacitance increase due to back-end-of-line (BEOL) dielectric cladding. A low-noise amplifier input stage is designed with optimum network design for a noise matched input and an inductive peaking output. The input stage shows up to 4-dB gain and 2.5-dB noise figure (NF), at 60 GHz. Utilizing gate-length scaling in the circuit environment, the obtained normalized intrinsic gate capacitance value of 0.34-aF/nm gate length, per NW, corresponds well to the predicted theoretical value, demonstrating the circuit's ability to provide intrinsic device parameters. This is the first mm-wave validation of noise models for III-V LNW MOSFETs. The results demonstrate the potential for utilization of the technology platform for low-noise applications.</p>}},
  author       = {{Andric, Stefan and Lindelow, Fredrik and Fhager, Lars Ohlsson and Lind, Erik and Wernersson, Lars Erik}},
  issn         = {{0018-9480}},
  keywords     = {{Back-end-of-line (BEOL); capacitance modeling; Dielectrics; front-end-of-line (FEOL); III-V.; InGaAs; lateral; LNA; Logic gates; MOSFET; nanowire (NW); NW circuits; Parasitic capacitance; Photomicrography; Radio frequency; Semiconductor device modeling}},
  language     = {{eng}},
  number       = {{2}},
  pages        = {{1284--1291}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  series       = {{IEEE Transactions on Microwave Theory and Techniques}},
  title        = {{Lateral III-V Nanowire MOSFETs in Low-Noise Amplifier Stages}},
  url          = {{http://dx.doi.org/10.1109/TMTT.2021.3124088}},
  doi          = {{10.1109/TMTT.2021.3124088}},
  volume       = {{70}},
  year         = {{2022}},
}