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Vertical Gate-All-Around Nanowire GaSb-InAs Core-Shell n-Type Tunnel FETs

Vasen, T.; Ramvall, P. LU ; Afzalian, A.; Doornbos, G.; Holland, M.; Thelander, C. LU ; Dick, K. A. LU ; Wernersson, L. E. LU and Passlack, M. (2019) In Scientific Reports 9(1).
Abstract

Tunneling Field-Effect Transistors (TFET) are one of the most promising candidates for future low-power CMOS applications including mobile and Internet of Things (IoT) products. A vertical gate-all-around (VGAA) architecture with a core shell (C-S) structure is the leading contender to meet CMOS footprint requirements while simultaneously delivering high current drive for high performance specifications and subthreshold swing below the Boltzmann limit for low power operation. In this work, VGAA nanowire GaSb/InAs C-S TFETs are demonstrated experimentally for the first time with key device properties of subthreshold swing S = 40 mV/dec (Vd = 10 mV) and current drive up to 40 μA/wire (Vd = 0.3 V, diameter d = 50 nm)... (More)

Tunneling Field-Effect Transistors (TFET) are one of the most promising candidates for future low-power CMOS applications including mobile and Internet of Things (IoT) products. A vertical gate-all-around (VGAA) architecture with a core shell (C-S) structure is the leading contender to meet CMOS footprint requirements while simultaneously delivering high current drive for high performance specifications and subthreshold swing below the Boltzmann limit for low power operation. In this work, VGAA nanowire GaSb/InAs C-S TFETs are demonstrated experimentally for the first time with key device properties of subthreshold swing S = 40 mV/dec (Vd = 10 mV) and current drive up to 40 μA/wire (Vd = 0.3 V, diameter d = 50 nm) while dimensions including core diameter d, shell thickness and gate length are scaled towards CMOS requirements. The experimental data in conjunction with TCAD modeling reveal interface trap density requirements to reach industry standard off-current specifications.

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author
organization
publishing date
type
Contribution to journal
publication status
published
subject
in
Scientific Reports
volume
9
issue
1
publisher
Nature Publishing Group
external identifiers
  • scopus:85060140819
ISSN
2045-2322
DOI
10.1038/s41598-018-36549-z
language
English
LU publication?
yes
id
66fcfd0e-b1ac-44df-af6a-b2327e9ca8bc
date added to LUP
2019-01-28 14:44:37
date last changed
2019-02-20 11:44:46
@article{66fcfd0e-b1ac-44df-af6a-b2327e9ca8bc,
  abstract     = {<p>Tunneling Field-Effect Transistors (TFET) are one of the most promising candidates for future low-power CMOS applications including mobile and Internet of Things (IoT) products. A vertical gate-all-around (VGAA) architecture with a core shell (C-S) structure is the leading contender to meet CMOS footprint requirements while simultaneously delivering high current drive for high performance specifications and subthreshold swing below the Boltzmann limit for low power operation. In this work, VGAA nanowire GaSb/InAs C-S TFETs are demonstrated experimentally for the first time with key device properties of subthreshold swing S = 40 mV/dec (V<sub>d</sub> = 10 mV) and current drive up to 40 μA/wire (V<sub>d</sub> = 0.3 V, diameter d = 50 nm) while dimensions including core diameter d, shell thickness and gate length are scaled towards CMOS requirements. The experimental data in conjunction with TCAD modeling reveal interface trap density requirements to reach industry standard off-current specifications.</p>},
  articleno    = {202},
  author       = {Vasen, T. and Ramvall, P. and Afzalian, A. and Doornbos, G. and Holland, M. and Thelander, C. and Dick, K. A. and Wernersson, L. E. and Passlack, M.},
  issn         = {2045-2322},
  language     = {eng},
  month        = {01},
  number       = {1},
  publisher    = {Nature Publishing Group},
  series       = {Scientific Reports},
  title        = {Vertical Gate-All-Around Nanowire GaSb-InAs Core-Shell n-Type Tunnel FETs},
  url          = {http://dx.doi.org/10.1038/s41598-018-36549-z},
  volume       = {9},
  year         = {2019},
}