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The impact of hetero-junction and oxide-interface traps on the performance of InAs/Si and InAs/GaAsSb nanowire tunnel FETs

Schenk, A. ; Sant, S. ; Moselund, K. ; Riel, H. ; Memisevic, E. LU and Wernersson, L. E. LU (2017) 2017 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2017 2017-September. p.273-276
Abstract

Fabricated InAs/Si and InAs/GaAsSb vertical nanowire tunnel FETs are analyzed by physics-based TCAD with emphasis on the impact of hetero-junction and oxide-interface traps on their performance. After careful fitting of a minimum set of parameters, the effects of diameter scaling and gate alignment are predicted. Trap-assisted tunneling at the oxide interface is suppressed by scaling the diameter into the volume-inversion regime. Gate alignment steepens the slope and increases the ON-current. The 'trap-tolerant' device geometry can result in a small sub-threshold swing despite commonly present trap concentrations.

Please use this url to cite or link to this publication:
author
; ; ; ; and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
nanowire TFETs, sub-thermal slope, TCAD, trap- A ssisted tunneling
host publication
2017 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2017
volume
2017-September
article number
8085317
pages
4 pages
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
conference name
2017 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2017
conference location
Kamakura, Japan
conference dates
2017-09-07 - 2017-09-09
external identifiers
  • scopus:85039070039
ISBN
9784863486102
DOI
10.23919/SISPAD.2017.8085317
language
English
LU publication?
yes
id
938dabed-374c-4eea-aded-e5298046f033
date added to LUP
2018-01-08 12:48:45
date last changed
2022-04-25 04:56:16
@inproceedings{938dabed-374c-4eea-aded-e5298046f033,
  abstract     = {{<p>Fabricated InAs/Si and InAs/GaAsSb vertical nanowire tunnel FETs are analyzed by physics-based TCAD with emphasis on the impact of hetero-junction and oxide-interface traps on their performance. After careful fitting of a minimum set of parameters, the effects of diameter scaling and gate alignment are predicted. Trap-assisted tunneling at the oxide interface is suppressed by scaling the diameter into the volume-inversion regime. Gate alignment steepens the slope and increases the ON-current. The 'trap-tolerant' device geometry can result in a small sub-threshold swing despite commonly present trap concentrations.</p>}},
  author       = {{Schenk, A. and Sant, S. and Moselund, K. and Riel, H. and Memisevic, E. and Wernersson, L. E.}},
  booktitle    = {{2017 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2017}},
  isbn         = {{9784863486102}},
  keywords     = {{nanowire TFETs; sub-thermal slope; TCAD; trap- A ssisted tunneling}},
  language     = {{eng}},
  month        = {{10}},
  pages        = {{273--276}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  title        = {{The impact of hetero-junction and oxide-interface traps on the performance of InAs/Si and InAs/GaAsSb nanowire tunnel FETs}},
  url          = {{http://dx.doi.org/10.23919/SISPAD.2017.8085317}},
  doi          = {{10.23919/SISPAD.2017.8085317}},
  volume       = {{2017-September}},
  year         = {{2017}},
}