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High Frequency Performance of Vertical InAs Nanowire MOSFET

Lind, Erik LU orcid ; Egard, Mikael LU ; Johansson, Sofia LU ; Johansson, Anne-Charlotte ; Borg, Mattias LU orcid ; Thelander, Claes LU ; Persson, Karl-Magnus LU ; Dey, Anil LU and Wernersson, Lars-Erik LU (2010) 22nd International Conference on Indium Phosphide and Related Materials
Abstract
We report on RF characterization of vertical, 100-nm-gate length InAs nanowire MOSFETs, utilizing wrap-gate technology and Al2O3 high-kappa gate oxide. The transistors show f(t)=5.6 GHz and f(max)=22 GHz, mainly limited by parasitic capacitances. The RF device performance is described using a hybrid-pi model taking hole generation at the drain into account. Electrostatic modeling of the parasitic capacitances for arrays of vertical nanowires indicates that a strong reduction in extrinsic capacitances can be achieved for devices with a small inter-wire separation.
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author
; ; ; ; ; ; ; and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
host publication
2010 22Nd International Conference On Indium Phosphide And Related Materials (Iprm)
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
conference name
22nd International Conference on Indium Phosphide and Related Materials
conference dates
2010-05-31 - 2010-06-04
external identifiers
  • wos:000287417700027
  • scopus:77955952765
ISSN
1092-8669
ISBN
978-1-4244-5919-3
DOI
10.1109/ICIPRM.2010.5516010
language
English
LU publication?
yes
id
b0e90fc6-071d-499c-80cc-2399e8a0cfd1 (old id 1859551)
date added to LUP
2016-04-01 13:33:21
date last changed
2025-10-14 11:12:52
@inproceedings{b0e90fc6-071d-499c-80cc-2399e8a0cfd1,
  abstract     = {{We report on RF characterization of vertical, 100-nm-gate length InAs nanowire MOSFETs, utilizing wrap-gate technology and Al2O3 high-kappa gate oxide. The transistors show f(t)=5.6 GHz and f(max)=22 GHz, mainly limited by parasitic capacitances. The RF device performance is described using a hybrid-pi model taking hole generation at the drain into account. Electrostatic modeling of the parasitic capacitances for arrays of vertical nanowires indicates that a strong reduction in extrinsic capacitances can be achieved for devices with a small inter-wire separation.}},
  author       = {{Lind, Erik and Egard, Mikael and Johansson, Sofia and Johansson, Anne-Charlotte and Borg, Mattias and Thelander, Claes and Persson, Karl-Magnus and Dey, Anil and Wernersson, Lars-Erik}},
  booktitle    = {{2010 22Nd International Conference On Indium Phosphide And Related Materials (Iprm)}},
  isbn         = {{978-1-4244-5919-3}},
  issn         = {{1092-8669}},
  language     = {{eng}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  title        = {{High Frequency Performance of Vertical InAs Nanowire MOSFET}},
  url          = {{http://dx.doi.org/10.1109/ICIPRM.2010.5516010}},
  doi          = {{10.1109/ICIPRM.2010.5516010}},
  year         = {{2010}},
}