An Efficient Approach to SoC Wrapper Design, TAM Configuration and Test Scheduling
Pouget, Julien ; Larsson, Erik LU
; Peng, Zebo
; Flottes, Marie-Lise
and Rouzeyre, Bruno
(2003)
IEEE European Test Workshop 2003 ETW03
p.51-56
- Abstract
- Test application time and core accessibility are two major issues in System-On-Chip (SOC) testing. The test application time must be minimised, and a test access mechanism (TAM) must be developed to transport test data to and from the cores. In this paper we present an approach to design a test interface (wrapper) at core level taking into account the P1500 restrictions, and to design a TAM architecture and its associated test schedule using a fast and efficient heuristic. A useful and new feature of our approach is that it supports also the testing of interconnections while considering power dissipation, test conflicts and precedence constraints. Another feature of our approach is that the TAM is designed with a central bus architecture,... (More)
- Test application time and core accessibility are two major issues in System-On-Chip (SOC) testing. The test application time must be minimised, and a test access mechanism (TAM) must be developed to transport test data to and from the cores. In this paper we present an approach to design a test interface (wrapper) at core level taking into account the P1500 restrictions, and to design a TAM architecture and its associated test schedule using a fast and efficient heuristic. A useful and new feature of our approach is that it supports also the testing of interconnections while considering power dissipation, test conflicts and precedence constraints. Another feature of our approach is that the TAM is designed with a central bus architecture, which is a generalisation of the TestBus architecture. The advantages and drawbacks of our approach are discussed, and the proposed architecture and heuristic are validated with experiments. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/2341129
- author
- Pouget, Julien
; Larsson, Erik
LU
; Peng, Zebo
; Flottes, Marie-Lise
and Rouzeyre, Bruno
- publishing date
- 2003
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- keywords
- test application time, system-on-chip, SOC, wrapper, test access mechanism, TAM, P1500 restrictions, TestBus architecture, test conflicts
- host publication
- [Host publication title missing]
- pages
- 51 - 56
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- IEEE European Test Workshop 2003 ETW03
- conference location
- Maastricht, Netherlands
- conference dates
- 2003-05-25 - 2003-05-28
- external identifiers
-
- scopus:84942925785
- ISSN
- 1530-1877
- ISBN
- 0-7695-1908-3
- DOI
- 10.1109/ETW.2003.1231668
- language
- English
- LU publication?
- no
- id
- c05a97b1-def6-4fb3-9a74-102bccfda344 (old id 2341129)
- date added to LUP
- 2016-04-01 16:49:57
- date last changed
- 2022-01-28 22:28:36
@inproceedings{c05a97b1-def6-4fb3-9a74-102bccfda344,
abstract = {{Test application time and core accessibility are two major issues in System-On-Chip (SOC) testing. The test application time must be minimised, and a test access mechanism (TAM) must be developed to transport test data to and from the cores. In this paper we present an approach to design a test interface (wrapper) at core level taking into account the P1500 restrictions, and to design a TAM architecture and its associated test schedule using a fast and efficient heuristic. A useful and new feature of our approach is that it supports also the testing of interconnections while considering power dissipation, test conflicts and precedence constraints. Another feature of our approach is that the TAM is designed with a central bus architecture, which is a generalisation of the TestBus architecture. The advantages and drawbacks of our approach are discussed, and the proposed architecture and heuristic are validated with experiments.}},
author = {{Pouget, Julien and Larsson, Erik and Peng, Zebo and Flottes, Marie-Lise and Rouzeyre, Bruno}},
booktitle = {{[Host publication title missing]}},
isbn = {{0-7695-1908-3}},
issn = {{1530-1877}},
keywords = {{test application time; system-on-chip; SOC; wrapper; test access mechanism; TAM; P1500 restrictions; TestBus architecture; test conflicts}},
language = {{eng}},
pages = {{51--56}},
publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
title = {{An Efficient Approach to SoC Wrapper Design, TAM Configuration and Test Scheduling}},
url = {{http://dx.doi.org/10.1109/ETW.2003.1231668}},
doi = {{10.1109/ETW.2003.1231668}},
year = {{2003}},
}