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A 4F2 Vertical Gate-all-around Nanowire Compute-in-memory Device Integrated in (1T1R) Cross-Point Arrays on Silicon

Mamidala, Saketh, Ram LU orcid ; Persson, Karl-Magnus LU and Wernersson, Lars-Erik LU (2022) 2022 IEEE Silicon Nanoelectronics Workshop (SNW) p.1-2
Abstract
Complete 4F2 vertical nanowire (VNW) 1T1R cells with 106 cycles switching endurance and with a demonstrated capability of performing Boolean logic are fabricated and characterized in cross-point arrays. The performance of the vertical 1T1R cell is benefited from using the same III-V/high- k interface both for the vertical GAA MOSFET selector as well as the ReRAM. In this paper, we also compare the InAs nanowire implementation to a nanowire with an InGaAs top segment to utilize the relatively larger bandgap of InGaAs to reduce sneak-path leakage currents.
Please use this url to cite or link to this publication:
author
; and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
host publication
IEEE Silicon Nanoelectronics Workshop (SNW)
pages
1 - 2
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
conference name
2022 IEEE Silicon Nanoelectronics Workshop (SNW)
conference location
Honolulu, United States
conference dates
2022-06-11 - 2022-06-12
external identifiers
  • scopus:85141074950
ISBN
978-1-6654-5979-2
DOI
10.1109/SNW56633.2022.9889066
language
English
LU publication?
yes
id
e04de5eb-cb35-4091-a48c-be228d452685
date added to LUP
2022-09-30 15:58:10
date last changed
2023-11-21 05:04:09
@inproceedings{e04de5eb-cb35-4091-a48c-be228d452685,
  abstract     = {{Complete 4F2 vertical nanowire (VNW) 1T1R cells with 10<sup>6</sup> cycles switching endurance and with a demonstrated capability of performing Boolean logic are fabricated and characterized in cross-point arrays. The performance of the vertical 1T1R cell is benefited from using the same III-V/high- k interface both for the vertical GAA MOSFET selector as well as the ReRAM. In this paper, we also compare the InAs nanowire implementation to a nanowire with an InGaAs top segment to utilize the relatively larger bandgap of InGaAs to reduce sneak-path leakage currents.}},
  author       = {{Mamidala, Saketh, Ram and Persson, Karl-Magnus and Wernersson, Lars-Erik}},
  booktitle    = {{IEEE Silicon Nanoelectronics Workshop (SNW)}},
  isbn         = {{978-1-6654-5979-2}},
  language     = {{eng}},
  month        = {{09}},
  pages        = {{1--2}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  title        = {{A 4F<sup>2</sup> Vertical Gate-all-around Nanowire Compute-in-memory Device Integrated in (1T1R) Cross-Point Arrays on Silicon}},
  url          = {{http://dx.doi.org/10.1109/SNW56633.2022.9889066}},
  doi          = {{10.1109/SNW56633.2022.9889066}},
  year         = {{2022}},
}