Low Trap Density in InAs/High-k Nanowire Gate Stacks with Optimized Growth and Doping Conditions
(2016) In Nano Letters 16(4). p.2418-2425- Abstract
In this paper, we correlate the growth of InAs nanowires with the detailed interface trap density (Dit) profile of the vertical wrap-gated InAs/high-k nanowire semiconductor-dielectric gate stack. We also perform the first detailed characterization and optimization of the influence of the in situ doping supplied during the nanowire epitaxial growth on the sequential transistor gate stack quality. Results show that the intrinsic nanowire channels have a significant reduction in Dit as compared to planar references. It is also found that introducing tetraethyltin (TESn) doping during nanowire growth severely degrades the Dit profile. By adopting a high temperature, low V/III ratio tailored growth scheme,... (More)
In this paper, we correlate the growth of InAs nanowires with the detailed interface trap density (Dit) profile of the vertical wrap-gated InAs/high-k nanowire semiconductor-dielectric gate stack. We also perform the first detailed characterization and optimization of the influence of the in situ doping supplied during the nanowire epitaxial growth on the sequential transistor gate stack quality. Results show that the intrinsic nanowire channels have a significant reduction in Dit as compared to planar references. It is also found that introducing tetraethyltin (TESn) doping during nanowire growth severely degrades the Dit profile. By adopting a high temperature, low V/III ratio tailored growth scheme, the influence of doping is minimized. Finally, characterization using a unique frequency behavior of the nanowire capacitance-voltage (C-V) characteristics reveals a change of the dopant incorporation mechanism as the growth condition is changed.
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- author
- Wu, Jun LU ; Babadi, Aein Shiri LU ; Jacobsson, Daniel LU ; Colvin, Jovana LU ; Yngman, Sofie LU ; Timm, Rainer LU ; Lind, Erik LU and Wernersson, Lars Erik LU
- organization
- publishing date
- 2016-04-13
- type
- Contribution to journal
- publication status
- published
- subject
- keywords
- C-V, D, growth, doping, crystalline phase, Nanowire
- in
- Nano Letters
- volume
- 16
- issue
- 4
- pages
- 8 pages
- publisher
- The American Chemical Society (ACS)
- external identifiers
-
- scopus:84964854645
- pmid:26978479
- wos:000374274600043
- ISSN
- 1530-6984
- DOI
- 10.1021/acs.nanolett.5b05253
- language
- English
- LU publication?
- yes
- id
- e69832d2-c3c3-43e8-a533-982438c49ab8
- date added to LUP
- 2016-07-08 10:03:40
- date last changed
- 2024-12-15 06:56:29
@article{e69832d2-c3c3-43e8-a533-982438c49ab8, abstract = {{<p>In this paper, we correlate the growth of InAs nanowires with the detailed interface trap density (D<sub>it</sub>) profile of the vertical wrap-gated InAs/high-k nanowire semiconductor-dielectric gate stack. We also perform the first detailed characterization and optimization of the influence of the in situ doping supplied during the nanowire epitaxial growth on the sequential transistor gate stack quality. Results show that the intrinsic nanowire channels have a significant reduction in D<sub>it</sub> as compared to planar references. It is also found that introducing tetraethyltin (TESn) doping during nanowire growth severely degrades the D<sub>it</sub> profile. By adopting a high temperature, low V/III ratio tailored growth scheme, the influence of doping is minimized. Finally, characterization using a unique frequency behavior of the nanowire capacitance-voltage (C-V) characteristics reveals a change of the dopant incorporation mechanism as the growth condition is changed.</p>}}, author = {{Wu, Jun and Babadi, Aein Shiri and Jacobsson, Daniel and Colvin, Jovana and Yngman, Sofie and Timm, Rainer and Lind, Erik and Wernersson, Lars Erik}}, issn = {{1530-6984}}, keywords = {{C-V; D, growth, doping, crystalline phase; Nanowire}}, language = {{eng}}, month = {{04}}, number = {{4}}, pages = {{2418--2425}}, publisher = {{The American Chemical Society (ACS)}}, series = {{Nano Letters}}, title = {{Low Trap Density in InAs/High-k Nanowire Gate Stacks with Optimized Growth and Doping Conditions}}, url = {{http://dx.doi.org/10.1021/acs.nanolett.5b05253}}, doi = {{10.1021/acs.nanolett.5b05253}}, volume = {{16}}, year = {{2016}}, }