Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si
Berg, Martin LU ; Persson, Karl-Magnus LU ; Kilpi, Olli-Pekka LU ; Svensson, Johannes LU ; Lind, Erik LU
and Wernersson, Lars-Erik
LU
(2016)
61st IEEE International Electron Devices Meeting, IEDM 2015
2016-February.
- Abstract
In this work, we present a novel self-aligned gate-last fabrication process for vertical nanowire metal-oxide-semiconductor field-effect transistors. The fabrication method allows for exposure dose-defined gate lengths and a local diameter reduction of the intrinsic channel segment, while maintaining thicker highly doped access regions. Using this process, InAs nanowire transistors combining good on-and off-performance are fabricated demonstrating Q = gm,max/SS = 8.2, which is higher than any previously reported vertical nanowire MOSFET.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/ef8834bb-39fb-4a50-90f2-98797f0ba7a8
- author
- Berg, Martin
LU
; Persson, Karl-Magnus
LU
; Kilpi, Olli-Pekka
LU
; Svensson, Johannes
LU
; Lind, Erik
LU
and Wernersson, Lars-Erik
LU
- organization
- publishing date
- 2016-02-16
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- host publication
- Technical Digest - International Electron Devices Meeting, IEDM
- volume
- 2016-February
- article number
- 7409806
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- 61st IEEE International Electron Devices Meeting, IEDM 2015
- conference location
- Washington, United States
- conference dates
- 2015-12-07 - 2015-12-09
- external identifiers
-
- scopus:84964040111
- ISBN
- 9781467398930
- DOI
- 10.1109/IEDM.2015.7409806
- language
- English
- LU publication?
- yes
- id
- ef8834bb-39fb-4a50-90f2-98797f0ba7a8
- date added to LUP
- 2016-06-16 10:30:06
- date last changed
- 2024-05-31 08:40:38
@inproceedings{ef8834bb-39fb-4a50-90f2-98797f0ba7a8,
abstract = {{<p>In this work, we present a novel self-aligned gate-last fabrication process for vertical nanowire metal-oxide-semiconductor field-effect transistors. The fabrication method allows for exposure dose-defined gate lengths and a local diameter reduction of the intrinsic channel segment, while maintaining thicker highly doped access regions. Using this process, InAs nanowire transistors combining good on-and off-performance are fabricated demonstrating Q = gm,max/SS = 8.2, which is higher than any previously reported vertical nanowire MOSFET.</p>}},
author = {{Berg, Martin and Persson, Karl-Magnus and Kilpi, Olli-Pekka and Svensson, Johannes and Lind, Erik and Wernersson, Lars-Erik}},
booktitle = {{Technical Digest - International Electron Devices Meeting, IEDM}},
isbn = {{9781467398930}},
language = {{eng}},
month = {{02}},
publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
title = {{Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si}},
url = {{https://lup.lub.lu.se/search/files/25111022/IEDM_Proof_extended_abstract.pdf}},
doi = {{10.1109/IEDM.2015.7409806}},
volume = {{2016-February}},
year = {{2016}},
}