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- 2015
-
Mark
Low Power Analog and Digital (7,5) Convolutional Decoders in 65 nm CMOS
- Contribution to journal › Article
- 2014
-
Mark
Low Power Decoding Circuits for Ultra Portable Devices
(2014)
- Thesis › Doctoral thesis (monograph)
-
Mark
Ultra low power transceivers for wireless sensors and body area networks
(2014) 8th International Symposium on Medical Information and Communication Technology (ISMICT)
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2013
-
Mark
A 3 mu W 500 kb/s Ultra Low Power Analog Decoder with Digital I/O in 65 nm CMOS
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 3 uW 500 kb/s Ultra Low Power Analog Decoder with Digital I/O in 65 nm CMOS
(2013) International Conference on Electronics and Communication Systems (ICECS)
- Contribution to conference › Paper, not in proceeding
-
Mark
Analog and Digital Approaches for an Energy Efficient Low Complexity Channel Decoder
(2013) IEEE International Symposium on Circuits and Systems (ISCAS), 2013 In Proceedings - IEEE International Symposium on Circuits and Systems p.1564-1567
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Analog and Digital Design Alternatives for a Low Complexity and Power Constraint Decoder
(2013)
- Contribution to conference › Paper, not in proceeding
- 2012
-
Mark
A receiver architecture for devices in wireless body area networks
(2012) In IEEE Journal on Emerging and Selected Topics in Circuits and Systems
- Contribution to journal › Article
- 2011
-
Mark
Physical implementation of analog circuits assisted by conventional digital place and route methods
(2011) CDNLive! EMEA, 2011
- Contribution to conference › Other
-
Mark
An Analog (7,5) Convolutional Decoder in 65 nm CMOS for Low Power Wireless Applications
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
