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- 2009
-
Mark
On Minimization of Peak Power for Scan Circuit during Test
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Fault-tolerant average execution time optimization for general-purpose multi-processor system-on-chips
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Generation of Minimal Leakage Input Vectors with Constrained NBTI Degradation
(
- Contribution to conference › Paper, not in proceeding
-
Mark
Power Efficient Redundant Execution for Chip Multiprocessors
(
- Contribution to conference › Paper, not in proceeding
-
Mark
An Even-Odd DFD Technique for Scan Chain Diagnosis
2009) Workshop on RTL and High Level Testing (WRTLT)(
- Contribution to conference › Paper, not in proceeding
-
Mark
Scan Cell Reordering to Minimize Peak Power during Scan Testing of SoC
(
- Contribution to conference › Paper, not in proceeding
-
Mark
On Scan Chain Diagnosis for Intermittent Faults
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Capture Power Reduction for Modular System-on-Chip Test
2009) IEEE/VSI VLSI Design and Test Symposium (VDAT)(
- Contribution to conference › Paper, not in proceeding
-
Mark
Thermal Aware Test Scheduling for Stacked Multi-Chip-Modules
2009) DATE 2009 Friday Workshop on 3D Integration - Technology, Architecture, Design, Automation, and Tes(
- Contribution to conference › Paper, not in proceeding
- 2008
-
Mark
Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding