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- 2008
-
Mark
An Integrated System-on-Chip Test Framework
2008) p.439-454(
- Chapter in Book/Report/Conference proceeding › Book chapter
-
Mark
Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2007
-
Mark
Optimized Integration of Test Compression and Sharing for SOC Testing
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint
2007) p.221-244(
- Chapter in Book/Report/Conference proceeding › Book chapter
- 2003
-
Mark
Buffer and Controller Minimization for Time-Constrained Testing of System-On-Chip
2003) 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems DFT03 p.385-392(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
SOC Test Time Minimization Under Multiple Constraints
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
An Efficient Approach to SoC Wrapper Design, TAM Configuration and Test Scheduling
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2002
-
Mark
An Integrated Framework for the Design and Optimization of SOC Test Solutions
(
- Contribution to journal › Article
-
Mark
An Integrated Framework for the Design and Optimization of SOC Test Solutions
2002) p.21-36(
- Chapter in Book/Report/Conference proceeding › Book chapter