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- 2010
-
Mark
Efficient Embedding of Deterministic Test Data
2010) Swedish SoC Conference 2010(
- Contribution to conference › Paper, not in proceeding
-
Mark
Checking Pipelined Distributed Global Properties for Post-silicon Debug
2010) IEEE Eleventh Workshop on RTL and High Level Testing, 2010(
- Contribution to conference › Paper, not in proceeding
-
Mark
Study on Combined Test-Data Compression and Test Planning for Testing of Modular SoCs
2010)(
- Chapter in Book/Report/Conference proceeding › Book chapter
-
Mark
Power Constrained Test Scheduling for 3D Stacked Chips: poster
2010) 1st IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits(
- Contribution to conference › Poster
- 2009
-
Mark
Power-Aware System-Level DfT and Test Planning
2009)(
- Chapter in Book/Report/Conference proceeding › Book chapter
-
Mark
An Even-Odd DFD Technique for Scan Chain Diagnosis
2009) Workshop on RTL and High Level Testing (WRTLT)(
- Contribution to conference › Paper, not in proceeding
-
Mark
Fault-Tolerant Average Execution Time Optimization for System-On-Chips
2009) Frontiers of High Performance Embedded Computing(
- Contribution to conference › Paper, not in proceeding
-
Mark
Deterministic Scan-Chain Diagnosis for Intermittent Faults
2009) European Test Symposium, ETS 2009(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
On Minimization of Peak Power for Scan Circuit during Test
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Fault-tolerant average execution time optimization for general-purpose multi-processor system-on-chips
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding