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- 2010
-
Mark
On-line Techniques to Adjust and Optimize Checkpointing Frequency
2010) IEEE International Workshop on Realiability Aware System Design and Test (RASDAT 2010) p.29-33(
- Contribution to conference › Paper, not in proceeding
-
Mark
Test scheduling on IJTAG
2010) Nordic Test Forum (NTF 2010),(
- Contribution to conference › Paper, not in proceeding
-
Mark
Scan Cells Reordering to Minimize Peak Power During Test Cycle : A Graph Theoretic Approach
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Study on Combined Test-Data Compression and Test Planning for Testing of Modular SoCs
2010)(
- Chapter in Book/Report/Conference proceeding › Book chapter
-
Mark
Checking Pipelined Distributed Global Properties for Post-silicon Debug
2010) IEEE Eleventh Workshop on RTL and High Level Testing, 2010(
- Contribution to conference › Paper, not in proceeding
-
Mark
Efficient Embedding of Deterministic Test Data
2010) Swedish SoC Conference 2010(
- Contribution to conference › Paper, not in proceeding
-
Mark
Power Constrained Test Scheduling for 3D Stacked Chips: poster
2010) 1st IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits(
- Contribution to conference › Poster
- 2009
-
Mark
Power-Aware System-Level DfT and Test Planning
2009)(
- Chapter in Book/Report/Conference proceeding › Book chapter
-
Mark
Deterministic Scan-Chain Diagnosis for Intermittent Faults
2009) European Test Symposium, ETS 2009(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
On Minimization of Peak Power for Scan Circuit during Test
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding