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- 2013
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Mark
Analog and Digital Approaches for an Energy Efficient Low Complexity Channel Decoder
2013) IEEE International Symposium on Circuits and Systems (ISCAS), 2013 In Proceedings - IEEE International Symposium on Circuits and Systems p.1564-1567(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Ultra Low Energy Design Exploration of Digital Decimation Filters in 65 nm Dual-VT CMOS in the Sub-VT Domain
(
- Contribution to journal › Article
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Mark
A 1V SiGe Power Amplifier for 81-86 GHz E-band
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A 3 mu W 500 kb/s Ultra Low Power Analog Decoder with Digital I/O in 65 nm CMOS
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A 31.25/125MSps Continuous-Time Delta-Sigma ADC with 64/59dB SNDR in 130nm CMOS
2013) NORCHIP Conference, 2013(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
An LC-Based Tunable Low-Isolation Device for Adaptive Duplexers
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Performance evaluation of N-well/P-sub photodiodes in 65nm CMOS process
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A 3 uW 500 kb/s Ultra Low Power Analog Decoder with Digital I/O in 65 nm CMOS
2013) International Conference on Electronics and Communication Systems (ICECS)(
- Contribution to conference › Paper, not in proceeding
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Mark
Analog and Digital Design Alternatives for a Low Complexity and Power Constraint Decoder
2013)(
- Contribution to conference › Paper, not in proceeding
-
Mark
A 0.7 - 3.7 GHz Six Phase Receiver Front-End With Third Order Harmonic Rejection
2013) IEEE European Solid State Circuits Conference, ESSCIRC 2013(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding