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- 2013
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Mark
A Wide Bandwidth Fractional-N Synthesizer for LTE with Phase Noise Cancellation Using a Hybrid- -DAC and Charge Re-timing
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A 2-D GRO Vernier Time-to-Digital Converter with Large Input Range and Small Latency
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Class-D CMOS Oscillators
(
- Contribution to journal › Article
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Mark
A 2.7-6.1 GHz CMOS local oscillator based on frequency multiplication by 3/2
(
- Contribution to journal › Article
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Mark
A 90nm CMOS Gated-Ring-Oscillator-Based 2-Dimension Vernier Time-to-Digital Converter
2013) Norchip conference, 2012(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2012
-
Mark
An Analysis of 1/f Noise to Phase Noise Conversion in CMOS Harmonic Oscillators
(
- Contribution to journal › Article
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Mark
A 90nm CMOS Digital PLL Based on Vernier-Gated-Ring-Oscillator Time-to-Digital Converter
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Phase Noise Analysis of the Tuned-Input-Tuned-Output (TITO) Oscillator
(
- Contribution to journal › Article
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Mark
A 3.6mW, 90nm CMOS Gated-Vernier Time-to-Digital Converter with an Equivalent Resolution of 3.2ps
(
- Contribution to journal › Article
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Mark
Harmonic Rejection Mixer at ADC Input for Complex IF Dual Carrier Receiver Architecture
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding