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- 2008
-
Mark
Modeling and exploration of a reconfigurable architecture for digital holographic imaging
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A hybrid interconnect network-on-chip and a transaction level modeling approach for reconfigurable computing
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A generic hardware MAC for wireless personal area network platforms
2008) International Symposium on Wireless Personal Multimedia Communications (WPMC), 2008(
- Contribution to conference › Paper, not in proceeding
-
Mark
Reducing computational complexity of branch metric calculations in a trellis decoder
2008) International Symposium on Wireless Personal Multimedia Communications (WPMC), 2008(
- Contribution to conference › Paper, not in proceeding
-
Mark
A variable-rate Viterbi decoder in 130-nm CMOS: design, measurements, and cost of flexibility
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Modelling and exploration of a reconfigurable array using SystemC TLM
(
- Contribution to conference › Paper, not in proceeding
-
Mark
A hardware acceleration platform for digital holographic imaging
(
- Contribution to journal › Article
-
Mark
Optimization and implementation of a Viterbi decoder under flexibility constraints
(
- Contribution to journal › Article
-
Mark
Low-Complexity Binary Morphology Architectures with Flat Rectangular Structure Elements
(
- Contribution to journal › Article
- 2007
-
Mark
Implementing the G.723.1 speech codec using a coarse-grained reconfigurable coprocessor
2007) International Conference on Engineering of Reconfigurable System and Algorithms (ERSA), p.195-198(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding