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- 2010
-
Mark
Modification of SOVA-based Algorithms for Efficient Hardware Implementation
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2008
-
Mark
Reducing computational complexity of branch metric calculations in a trellis decoder
2008) International Symposium on Wireless Personal Multimedia Communications (WPMC), 2008(
- Contribution to conference › Paper, not in proceeding
-
Mark
A variable-rate Viterbi decoder in 130-nm CMOS: design, measurements, and cost of flexibility
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2007
-
Mark
Survivor path processing in Viterbi decoders using register exchange and traceforward
(
- Contribution to journal › Article
-
Mark
Trellis Decoding: From Algorithm to Flexible Architectures
2007) In Series of licentiate and doctoral theses(
- Thesis › Doctoral thesis (monograph)
- 2006
-
Mark
Architectural Optimization for Low power in a Reconfigurable UMTS filter
2006) International Symposium on Wireless Personal Multimedia Communications (WPMC), 2006(
- Contribution to conference › Paper, not in proceeding
- 2005
-
Mark
A manual on ASIC front to back end design flow
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Architectural considerations for rate-flexible trellis processing blocks
2005) IEEE International Symposium on Personal, Indoor and Mobile Radio Communications, 2005 p.1076-1080(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A hardware efficiency analysis for simplified trellis decoding blocks
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Teaching digital ASIC design to students with heterogeneoms previous knowledge
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding