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- 2013
-
Mark
Analog and Digital Design Alternatives for a Low Complexity and Power Constraint Decoder
2013)(
- Contribution to conference › Paper, not in proceeding
-
Mark
A 3 uW 500 kb/s Ultra Low Power Analog Decoder with Digital I/O in 65 nm CMOS
2013) International Conference on Electronics and Communication Systems (ICECS)(
- Contribution to conference › Paper, not in proceeding
- 2012
-
Mark
Reduced-Complexity Receivers for Strongly Narrowband Intersymbol Interference Introduced by Faster-than-Nyquist Signaling
(
- Contribution to journal › Article
-
Mark
Minimum Distance Analysis of a Certain Class of 2-D ISI Channels
(
- Contribution to journal › Article
-
Mark
A receiver architecture for devices in wireless body area networks
2012) In IEEE Journal on Emerging and Selected Topics in Circuits and Systems(
- Contribution to journal › Article
-
Mark
Best Rate 1/2 Convolutional Codes for Turbo Equalization with Severe ISI
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2011
-
Mark
Design and Implementation of Iterative Decoder for Faster-than-Nyquist Signaling Multicarrier systems
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
An Analog (7,5) Convolutional Decoder in 65 nm CMOS for Low Power Wireless Applications
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Transistor sizing for a 4-state current mode analog channel decoder in 65-nm CMOS
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2010
-
Mark
Design and Measurement of a Variable-Rate Viterbi Decoder in 130-nm Digital CMOS
(
- Contribution to journal › Article